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www.motorola.com/semiconductors hc s 08 microcontrollers mc 9 s 0 8 gb 6 0 /d r e v . 1 . 5 , 1 1 / 20 0 3 mc 9s08gb60 mc 9s08gb32 technical data mc 9s08gt60 mc 9s08gt32

motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical parameters which may be provided in motorola data sheets and/or speci fications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each custom er application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intende d, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such uninte nded or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against al l claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unautho rized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. document number mc9s08gb60/d ?otorola, inc., 2003 motorola 3 mc9s08gb/gt mc9s08gb/gt data sheet v1.5 8-/16-bit products division motorola, inc.
mc9s08gb/gt 4 motorola revision history to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://motorola.com/semiconductors the following revision history table summarizes changes contained in this document. this product incorporates superflash ? technology licensed from sst. motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ? motorola, inc., 2003 revision number revision date description of changes 1.0 4/25/2003 initial release 1.1 electricals change, appendix a only 1.2 electricals change, appendix a only 1.3 10/2/2003 added module version table; clari?ations 1.4 10/29/2003 fixed typos and made corrections and clari?ations 1.5 11/12/2003 added 1-mhz i dd values to electricals, appendix a
data sheet ?mc9s08gb60/d v1.5 motorola 5 mc9s08gb/gt list of sections section 1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 section 2 pins and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 section 3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 section 4 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 5 resets, interrupts, and system configuration . . . . . . . . . . . . . . . 63 section 6 internal clock generator (icg) module . . . . . . . . . . . . . . . . . . . . . 81 section 7 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 section 8 parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 section 9 keyboard interrupt (kbi) module . . . . . . . . . . . . . . . . . . . . . . . . . 149 section 10 timer/pwm (tpm) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 section 11 serial communications interface (sci) module. . . . . . . . . . . . . 171 section 12 serial peripheral interface (spi) module . . . . . . . . . . . . . . . . . . 191 section 13 inter-integrated circuit (iic) module . . . . . . . . . . . . . . . . . . . . . . 207 section 14 analog-to-digital converter (atd) module . . . . . . . . . . . . . . . . 221 section 15 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 appendix a electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 appendix b ordering information and mechanical drawings. . . . . . . . . . . 283
list of sections mc9s08gb/gt 6 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 7 mc9s08gb/gt table of contents section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 1.2.1 standard features of the hcs08 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.2 features of mc9s08gb/gt series of mcus. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.3 devices in the mc9s08gb/gt series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.3 mcu block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 system clock distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 section 2 pins and connections 2.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 2.2 device pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 recommended system connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.1 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2.3.4 background/mode select (ptg0/bkgd/ms). . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.5 general-purpose i/o and peripheral ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.6 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 section 3 modes of operation 3.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3.3 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 active background mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6.1 stop1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6.2 stop2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6.3 stop3 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6.4 active bdm enabled in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.6.5 lvd enabled in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.6.6 on-chip peripheral modules in stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
table of contents mc9s08gb/gt 8 motorola section 4 memory 4.1 mc9s08gb/gt memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.1 reset and interrupt vector assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2 register addresses and bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.4 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 4.4.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.2 program and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.3 program and erase command execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.4 burst program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.4.5 access errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.4.6 flash block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.4.7 vector redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.6 flash registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.6.1 flash clock divider register (fcdiv). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6.2 flash options register (fopt and nvopt) . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.6.3 flash configuration register (fcnfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6.4 flash protection register (fprot and nvprot) . . . . . . . . . . . . . . . . . . . . . . 59 4.6.5 flash status register (fstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6.6 flash command register (fcmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 section 5 resets, interrupts, and system configuration 5.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 5.3 mcu reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.4 computer operating properly (cop) watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5.1 interrupt stack frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.5.2 external interrupt request (irq) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.5.3 interrupt vectors, sources, and local masks . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.6 low-voltage detect (lvd) system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.6.1 power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.6.2 lvd reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.6.3 lvd interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.6.4 low-voltage warning (lvw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
data sheet ?mc9s08gb60/d v1.5 motorola 9 mc9s08gb/gt 5.7 real-time interrupt (rti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.8 reset, interrupt, and system control registers and control bits . . . . . . . . . . . . . . 70 5.8.1 interrupt pin request status and control register (irqsc) . . . . . . . . . . . . . . . . 70 5.8.2 system reset status register (srs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.8.3 system background debug force reset register (sbdfr). . . . . . . . . . . . . . . . 73 5.8.4 system options register (sopt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.8.5 system device identification register (sdidh, sdidl) . . . . . . . . . . . . . . . . . . . 75 5.8.6 system real-time interrupt status and control register (srtisc) . . . . . . . . . . 75 5.8.7 system power management status and control 1 register (spmsc1) . . . . . . . 77 5.8.8 system power management status and control 2 register (spmsc2) . . . . . . . 78 section 6 internal clock generator (icg) module 6.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 6.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.3 external clock connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.4 external crystal/resonator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.1 off mode (off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.2 self-clocked mode (scm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.3 fll engaged, internal clock (fei) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.4 fll bypassed, external clock (fbe) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.5 fll engaged, external clock (fee) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.6 fll lock and loss-of-lock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.7 fll loss-of-clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.8 clock mode requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.4 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4.2 example #1: external crystal = 32 khz, bus frequency = 4.19 mhz . . . . . . . . . 96 6.4.3 example #2: external crystal = 4 mhz, bus frequency = 20 mhz. . . . . . . . . . . 98 6.4.4 example #3: no external crystal connection, 5.4 mhz bus frequency . . . . . . 100 6.4.5 example #4: internal clock generator trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.5 icg registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
table of contents mc9s08gb/gt 10 motorola 6.5.1 icg control register 1 (icgc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.5.2 icg control register 2 (icgc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.5.3 icg status register 1 (icgs1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.5.4 icg status register 2 (icgs2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.5.5 icg filter registers (icgfltu, icgfltl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.5.6 icg trim register (icgtrm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 section 7 central processor unit (cpu) 7.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.3 programmer? model and cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.3.2 index register (h:x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.3.3 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.3.4 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.3.5 condition code register (ccr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.4 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.4.1 inherent addressing mode (inh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.4.2 relative addressing mode (rel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.4.3 immediate addressing mode (imm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.4.4 direct addressing mode (dir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.4.5 extended addressing mode (ext). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.4.6 indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.5 special operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.5.1 reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.5.2 interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.5.3 wait mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.5.4 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.5.5 bgnd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.6 hcs08 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 section 8 parallel input/output 8.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.3.1 port a and keyboard interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
data sheet ?mc9s08gb60/d v1.5 motorola 11 mc9s08gb/gt 8.3.2 port b and analog to digital converter inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.3.3 port c and sci2, iic, and high-current drivers . . . . . . . . . . . . . . . . . . . . . . . . 132 8.3.4 port d, tpm1 and tpm2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.3.5 port e, sci1, and spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.3.6 port f and high-current drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.3.7 port g, bkgd/ms, and oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.4 parallel i/o controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.4.1 data direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.4.2 internal pullup control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.4.3 slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.5 stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.6 parallel i/o registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.6.1 port a registers (ptad, ptape, ptase, and ptadd) . . . . . . . . . . . . . . . . . . 136 8.6.2 port b registers (ptbd, ptbpe, ptbse, and ptbdd) . . . . . . . . . . . . . . . . . . 138 8.6.3 port c registers (ptcd, ptcpe, ptcse, and ptcdd) . . . . . . . . . . . . . . . . . 139 8.6.4 port d registers (ptdd, ptdpe, ptdse, and ptddd) . . . . . . . . . . . . . . . . . 141 8.6.5 port e registers (pted, ptepe, ptese, and ptedd) . . . . . . . . . . . . . . . . . . 142 8.6.6 port f registers (ptfd, ptfpe, ptfse, and ptfdd) . . . . . . . . . . . . . . . . . . 144 8.6.7 port g registers (ptgd, ptgpe, ptgse, and ptgdd) . . . . . . . . . . . . . . . . . 145 section 9 keyboard interrupt (kbi) module 9.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.1.1 port a and keyboard interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.3 kbi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.4 keyboard interrupt (kbi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.4.1 pin enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.4.2 edge and level sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.4.3 kbi interrupt controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.5 kbi registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.5.1 kbi status and control register (kbisc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.5.2 kbi pin enable register (kbipe). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 section 10 timer/pwm (tpm) module 10.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 10.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5
table of contents mc9s08gb/gt 12 motorola 10.3 tpm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4.1 external tpm clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4.2 tpmxchn ?tpmx channel n i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.5.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.5.2 channel mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.5.3 center-aligned pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10.6 tpm interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.6.1 clearing timer interrupt flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.6.2 timer overflow interrupt description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.6.3 channel event interrupt description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.6.4 pwm end-of-duty-cycle events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.7 tpm registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.7.1 timer x status and control register (tpmxsc) . . . . . . . . . . . . . . . . . . . . . . . . 165 10.7.2 timer x counter registers (tpmxcnth:tpmxcntl). . . . . . . . . . . . . . . . . . . . 166 10.7.3 timer x counter modulo registers (tpmxmodh:tpmxmodl) . . . . . . . . . . . . 167 10.7.4 timer x channel n status and control register (tpmxcnsc) . . . . . . . . . . . . . 168 10.7.5 timer x channel value registers (tpmxcnvh:tpmxcnvl). . . . . . . . . . . . . . . 170 section 11 serial communications interface (sci) module 11.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 11.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 11.3 sci system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.4 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5 transmitter functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.1 transmitter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.2 send break and queued idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.6 receiver functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.6.1 receiver block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.6.2 data sampling technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.6.3 receiver wakeup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.7 interrupts and status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8 additional sci functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.8.1 8- and 9-bit data modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.9 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
data sheet ?mc9s08gb60/d v1.5 motorola 13 mc9s08gb/gt 11.9.1 loop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.9.2 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.10 sci registers and control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.10.1 sci x baud rate registers (scixbdh, scixbhl). . . . . . . . . . . . . . . . . . . . . . . 182 11.10.2 sci x control register 1 (scixc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.10.3 sci x control register 2 (scixc2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.10.4 sci x status register 1 (scixs1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.10.5 sci x status register 2 (scixs2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.10.6 sci x control register 3 (scixc3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.10.7 sci x data register (scixd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 section 12 serial peripheral interface (spi) module 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 12.2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.2.1 spi system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.2.2 spi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 12.2.3 spi baud rate generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.3.1 spi clock formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.3.2 spi pin controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12.3.3 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.3.4 mode fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.4 spi registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.4.1 spi control register 1 (spic1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.4.2 spi control register 2 (spic2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.4.3 spi baud rate register (spibr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.4.4 spi status register (spis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.4.5 spi data register (spid). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 section 13 inter-integrated circuit (iic) module 13.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 13.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 13.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 13.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 13.1.4 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
table of contents mc9s08gb/gt 14 motorola 13.2.1 iic protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 13.3 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 13.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 13.4.1 byte transfer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 13.4.2 address detect interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 13.4.3 arbitration lost interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5 iic registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5.1 iic address register (iica) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.5.2 iic frequency divider register (iicf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 13.5.3 iic control register (iicc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 13.5.4 iic status register (iics). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 13.5.5 iic data i/o register (iicd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 section 14 analog-to-digital converter (atd) module 14.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 14.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 14.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 14.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 14.2 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 14.3.1 mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14.3.2 sample and hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14.3.3 analog input multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.3.4 atd module accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.4 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 30 14.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 30 14.6 atd registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.6.1 atd control (atdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.6.2 atd status and control (atdsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.3 atd result data (atdrh, atdrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 14.6.4 atd pin enable (atdpe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 section 15 development support 15.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8
data sheet ?mc9s08gb60/d v1.5 motorola 15 mc9s08gb/gt 15.3 background debug controller (bdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.3.1 bkgd pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.3.2 communication details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.3.3 bdc commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 15.3.4 bdc hardware breakpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 15.4 on-chip debug system (dbg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.4.1 comparators a and b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.4.2 bus capture information and fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.4.3 change-of-flow information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.4.4 tag vs. force breakpoints and triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 15.4.5 trigger modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 15.4.6 hardware breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.5 registers and control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.5.1 bdc registers and control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.5.2 system background debug force reset register (sbdfr). . . . . . . . . . . . . . . 253 15.5.3 dbg registers and control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 appendix a electrical characteristics a.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 a.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 a.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 a.4 electrostatic discharge (esd) protection characteristics . . . . . . . . . . . . . . . . . . . 263 a.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 a.6 supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 a.7 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 a.8 internal clock generation module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 273 a.8.1 icg frequency specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 a.9 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 a.9.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 a.9.2 timer/pwm (tpm) module timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 a.9.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 a.10 flash specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 appendix b ordering information and mechanical drawings b.1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 b.2 mechanical drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
table of contents mc9s08gb/gt 16 motorola b.3 64-pin lqfp package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 b.4 44-pin qfp package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 b.5 42-pin sdip package drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
data sheet ?mc9s08gb60/d v1.5 motorola 17 mc9s08gb/gt section 1 introduction 1.1 overview the mc9s08gb/gt are members of the low-cost, high-performance hcs08 family of 8-bit microcontroller units (mcus). all mcus in the family use the enhanced hcs08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 features features have been organized to reflect: standard features of the hcs08 family features of the mc9s08gb/gt mcu 1.2.1 standard features of the hcs08 family 40-mhz hcs08 cpu (central processor unit) hc08 instruction set with added bgnd instruction background debugging system (see also the development support section) breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) debug module containing two comparators and nine trigger modes. eight deep fifo for storing change-of-flow addresses and event-only data. debug module supports both tag and force breakpoints. support for up to 32 interrupt/reset sources power-saving modes: wait plus three stops system protection features: optional computer operating properly (cop) reset low-voltage detection with reset or interrupt illegal opcode detection with reset illegal address detection with reset (some devices don? have illegal addresses) 1.2.2 features of mc9s08gb/gt series of mcus on-chip in-circuit programmable flash memory with block protection and security options (see table 1-1 for device specific information) on-chip random-access memory (ram) (see table 1-1 for device specific information) 8-channel, 10-bit analog-to-digital converter (atd)
introduction mc9s08gb/gt 18 motorola two serial communications interface modules (sci) serial peripheral interface module (spi) clock source options include crystal, resonator, external clock or internally generated clock with precision nvm trimming inter-integrated circuit bus module to operate up to 100 kbps (iic) one 3-channel and one 5-channel 16-bit timer/pulse width modulator (tpm) modules with selectable input capture, output compare, and edge-aligned pwm capability on each channel. each timer module may be configured for buffered, centered pwm (cpwm) on all channels (tpmx). 8-pin keyboard interrupt module (kbi) 16 high-current pins (limited by package dissipation) software selectable pullups on ports when used as input. selection is on an individual port bit basis. during output mode, pullups are disengaged. internal pullup on reset and irq pin to reduce customer system cost 56 general-purpose input/output (i/o) pins, depending on package selection 64-pin low-profile quad flat package (lqfp) ?mc9s08gbxx 44-pin quad flat package (qfp) ?mc9s08gtxx 42-pin shrink dual in-line package (sdip) ?mc9s08gtxx 1.2.3 devices in the mc9s08gb/gt series table 1-1 lists the devices available in the mc9s08gb/gt series and summarizes the differences among them. 1.3 mcu block diagrams these block diagrams shows the structure of the mc9s08gb/gt mcus. table 1-1 devices in the mc9s08gb/gt series device flash ram tpm i/o packages mc9s08gb60 60k 4k one 3-channel and one 5-channel 16-bit timer 56 64 lqfp mc9s08gb32 32k 2k one 3-channel and one 5-channel 16-bit timer 56 64 lqfp MC9S08GT60 60k 4k tw o 2-channel/16- bit timers 36 44 qfp 34 42 sdip mc9s08gt32 32k 2k tw o 2-channel/16- bit timers 36 44 qfp 34 42 sdip
data sheet ?mc9s08gb60/d v1.5 motorola 19 mc9s08gb/gt figure 1-1 mc9s08gbxx block diagram ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain both pullup and pulldown devices. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5 cpu bdc
introduction mc9s08gb/gt 20 motorola figure 1-2 mc9s08gtxx block diagram ptd3/tpm2ch0 ptd4/tpm2ch1 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc6 (note 6) ptc5 (note 6) ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gt60 = 4096 bytes) debug module (dbg) (gt60 = 61,268 bytes) hcs08 core notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. ptc[6:5] are not available on the 42-pin sdip package. 7. pins pta[7:4] contain both pullup and pulldown devices. pulldown available when kbi enabled (kbipn = 1). 8. only two timer channels per tpm are bonded out. all channels are available for use. note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) note 1 8 pta0/kbip0 8 ptb0/ad0 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g note 4 notes 1, 5 (gt32 = 32,768 bytes) (gt32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 7 note 1 (note 8) (note 8) cpu bdc
data sheet ?mc9s08gb60/d v1.5 motorola 21 mc9s08gb/gt table 1-2 lists the functional versions of the on-chip modules. 1.4 system clock distribution figure 1-3 system clock distribution diagram table 1-2 block versions module version analog-to-digital converter (atd) 3 internal clock generator (icg) 2 inter-integrated circuit (iic) 1 keyboard interrupt (kbi) 1 serial communications interface (sci) 1 serial peripheral interface (spi) 3 timer pulse-width modulator (tpm) 1 central processing unit (cpu) 2 tpm1 tpm2 iic sci1 sci2 spi bdc cpu atd ram flash icg icgout 2 ffe system logic busclk icglclk* atd has min and max frequency requirements. see atd section and flash has frequency requirements for program and erase operation. see appendix a. appendix a. control fixed freq clock (xclk) icgerclk rti * icglclk is the alternate bdc clock source for the mc9s08gb/gt.
introduction mc9s08gb/gt 22 motorola some of the modules inside the mcu have clock source choices. figure 1-3 shows a simplified clock connection diagram. the icg supplies the clock sources: icgout is an output of the icg module. it is either: the external crystal oscillator an external clock source the output of the digitally-controlled oscillator (dco) in the frequency-locked loop sub-module control bits inside the icg determine which source is connected. ffe is a control signal generated inside the icg. if the frequency of icgout > 4 the frequency of icgerclk, this signal is a logic 1 and the fixed-frequency clock will be the icgerclk. otherwise the fixed-frequency clock will be busclk. icglclk development tools can select this internal self-clocked source (~ 8 mhz) to speed up bdc communications in systems where the bus clock is slow. icgerclk ?external reference clock can be selected as the real-time interrupt clock source.
data sheet ?mc9s08gb60/d v1.5 motorola 23 mc9s08gb/gt section 2 pins and connections 2.1 introduction this section describes signals that connect to package pins. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 device pin assignment figure 2-1 mc9s08gbxx in 64-pin lqfp package ptc3/scl 1 2 3 4 5 6 7 8 ptc0/txd2 ptc1/rxd2 ptc4 ptc5 ptc6 ptc7 ptd0/tpm1ch0 v dd v ss pte7 pte6 pte5/spsck pte4/mosi v refh v refl ptf5 ptf6 ptf7 ptb2/ad2 ptb7/ad7 pta5/kbip5 ptf0 ptg6 v ssad v ddad ptf1 pta2/kbip2 pta6/kbip6 pta7/kbip7 43 42 41 40 39 38 18 19 20 21 22 23 50 51 52 53 54 55 17 32 33 49 48 64 9 ptf2 10 ptf3 11 ptf4 16 irq ptd1/tpm1ch1 24 ptd2/tpm1ch2 25 ptd3/tpm2ch0 26 ptd4/tpm2ch1 27 ptb6/ad6 37 ptb5/ad5 36 ptb4/ad4 35 ptb3/ad3 34 ptg0/bkgd/ms 56 ptg1/xtal 57 ptg2/extal 58 ptg3 59 ptc2/sda 12 pte0/txd1 13 14 15 pte1/rxd1 ptd5/tpm2ch2 28 29 30 31 pta0/kbip0 44 45 46 pta1/kbip1 47 ptg5 63 62 61 ptg4 60 reset ptg7 pte2/ ss pte3/miso ptd6/tpm2ch3 ptd7/tpm2ch4 ptb1/ad1 ptb0/ad0 pta4/kbip4 pta3/kbip3
pins and connections mc9s08gb/gt 24 motorola figure 2-2 mc9s08gtxx in 44-pin qfp package 44 34 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 12 23 reset pte0/txd1 pte1/rxd1 irq ptc0/txd2 ptc1/rxd2 ptc2/sda ptc3/scl ptc4 ptc5 ptc6 ptd1/tpm1ch1 ptd0/tpm1ch0 v dd v ss pte5/spsck pte4/mosi pte3/miso pte2/ ss ptd3/tpm2ch0 ptd4/tpm2ch1 ptb0/ad0 ptb6/ad6 ptb7/ad7 v refh v refl pta0/kbip0 ptb2/ad2 ptb3/ad3 ptb1/ad1 ptb4/ad4 ptb5/ad5 pta4/kbip4 pta5/kbip5 v ddad ptg2/extal ptg1/xtal ptg0/bkgd/ms v ssad pta1/kbip1 pta6/kbip6 pta7/kbip7 pta3/kbip3 pta2/kbip2
data sheet ?mc9s08gb60/d v1.5 motorola 25 mc9s08gb/gt figure 2-3 mc9s08gtxx in 42-pin sdip package 2.3 recommended system connections figure 2-4 shows pin connections that are common to almost all mc9s08gbxx application systems. mc9s08gtxx connections will be similar except for the amount of i/o pins available. a more detailed discussion of system connections follows. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 irq pte1/rxd1 pte0/txd1 v ddad ptc2/sda ptc3/scl ptc4 ptb5/ad5 ptb6/ad6 ptb7/ad7 v refh v refl pta0/kbip0 pta1/kbip1 pta2/kbip2 pta4/kbip4 pta3/kbip3 ptb4/ad4 pta5/kbip5 pta6/kbip6 pta7/kbip7 v ssad ptg0/bkgd/ms ptg1/xtal ptg2/extal reset ptc0/txd2 ptc1/rxd2 15 28 pte2/ ss ptb3/ad3 16 27 pte3/miso ptb2/ad2 17 26 pte4/mosi ptb1/ad1 18 25 pte5/spsck ptb0/ad0 19 24 v ss ptd4/tpm2ch1 20 23 v dd ptd3/tpm2ch0 21 22 ptd0/tpm1ch0 ptd1/tpm1ch1
pins and connections mc9s08gb/gt 26 motorola figure 2-4 basic system connections v dd v ss xtal extal bkgd/ms reset optional manual reset port a v dd 1 background header c2 c1 x1 r f r s c by 0.1 f c blk 10 f + 3 v + system power i/o and peripheral interface to system application pta0/kbip0 pta1/kbip1 pta2/kbip2 pta3/kbip3 pta4/kbip4 pta5/kbip5 pta6/kbip6 pta7/kbip7 v dd port b ptb0/ad0 ptb1/ad1 ptb2/ad2 ptb3/ad3 ptb4/ad4 ptb5/ad5 ptb6/ad6 ptb7/ad7 port c ptc0/txd2 ptc1/rxd2 ptc2/sda ptc3/scl ptc4 ptc5 ptc6 ptc7 port d ptd0/tpm1ch0 ptd1/tpm1ch1 ptd2/tpm1ch2 ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptd7/tpm2ch4 port e pte0/txd1 pte1/rxd1 pte2/ ss pte3/miso pte4/mosi pte5/spsck pte6 pte7 port g ptg0/bkdg/ms ptg1/xtal ptg2/extal ptg3 ptg4 ptg5 ptg6 ptg7 port f ptf0 ptf1 ptf2 ptf3 ptf4 ptf5 ptf6 ptf7 irq asynchronous interrupt input notes: 1. not required if using the internal oscillator option. 2. these are the same pins as ptg1 and ptg2. 3. bkgd/ms is the same pin as ptg0. note 1 note 2 note 2 note 3 mc9s08gbxx v ddad v ssad c byad 0.1 f v refl v refh
data sheet ?mc9s08gb60/d v1.5 motorola 27 mc9s08gb/gt 2.3.1 power v dd and v ss are the primary power supply pins for the mcu. this voltage source supplies power to all i/o buffer circuitry and to an internal voltage regulator. the internal voltage regulator provides regulated lower-voltage source to the cpu and other internal circuitry of the mcu. typically, application systems have two separate capacitors across the power pins. in this case, there should be a bulk electrolytic capacitor, such as a 10- f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1- f ceramic bypass capacitor located as close to the mcu power pins as practical to suppress high-frequency noise. v ddad and v ssad are the analog power supply pins for the mcu. this voltage source supplies power to the atd. a 0.1- f ceramic bypass capacitor should be located as close to the mcu power pins as practical to suppress high-frequency noise. 2.3.2 oscillator out of reset the mcu uses an internally generated clock (self-clocked mode ?f self_reset ) equivalent to about 8-mhz crystal rate. this frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. this mcu also contains a trimmable internal clock generator (icg) module that can be used to run the mcu. for more information on the icg, see the internal clock generator section. the oscillator in this mcu is a pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the range bit in the icgc1 register. rather than a crystal or ceramic resonator, an external oscillator can be connected to the extal input pin, and the xtal output pin must be left unconnected. refer to figure 2-4 for the following discussion. r s (when used) and r f should be low-inductance resistors such as carbon composition resistors. wire-wound resistors, and some metal film resistors, have too much inductance. c1 and c2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. r f is used to provide a bias path to keep the extal input in its linear range during crystal startup and its value is not generally critical. typical systems use 1 m ? to 10 m ? . higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. c1 and c2 are typically in the 5-pf to 25-pf range and are chosen to match the requirements of a specific crystal or resonator. be sure to take into account printed circuit board (pcb) capacitance and mcu pin capacitance when sizing c1 and c2. the crystal manufacturer typically specifies a load capacitance which is the series combination of c1 and c2 which are usually the same size. as a first-order approximation, use 10 pf as an estimate of combined pin and pcb capacitance for each oscillator pin (extal and xtal). 2.3.3 reset reset is a dedicated pin with a pullup device built in. it has input hysteresis, a high current output driver, and no output slew rate control. internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. this pin is normally connected to the standard 6-pin background
pins and connections mc9s08gb/gt 28 motorola debug connector so a development system can directly reset the mcu system. if desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for about 34 cycles of f self_reset , released, and sampled again about 38 cycles of f self_reset later. if reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry expects the reset pin sample to return a logic 1. if the pin is still low at this sample point, the reset is assumed to be from an external source. the reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (srs). never connect any significant capacitance to the reset pin because that would interfere with the circuit and sequence that detects the source of reset. if an external capacitance prevents the reset pin from rising to a valid logic 1 before the reset sample point, all resets will appear to be external resets. 2.3.4 background/mode select (ptg0/bkgd/ms) the background/mode select (bkgd/ms) shares its function with an i/o port pin. while in reset the pin functions as a mode select pin. immediately after reset rises the pin functions as the background pin and can be used for background debug communication. while functioning as a background/mode select pin the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. when used as an i/o port (ptg0) the pin is limited to output only. if nothing is connected to this pin, the mcu will enter normal operating mode at the rising edge of reset. if a debug system is connected to the 6-pin standard background debug header, it can hold bkgd/ms low during the rising edge of reset which forces the mcu to active background mode. the bkgd pin is used primarily for background debug controller (bdc) communications using a custom protocol that uses 16 clock cycles of the target mcu? bdc clock per bit time. the target mcu? bdc clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the bkgd/ms pin that could interfere with background serial communications. although the bkgd pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the bkgd pin. 2.3.5 general-purpose i/o and peripheral ports the remaining 55 pins are shared among general-purpose i/o and on-chip peripheral functions such as timers and serial i/o systems. (twenty of these pins are not bonded out on the 44-pin package and twenty-two are not bonded out on the 42-pin package.) immediately after reset, all 55 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. note: to avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float.
data sheet ?mc9s08gb60/d v1.5 motorola 29 mc9s08gb/gt for information about controlling these pins as general-purpose i/o pins, see the parallel input/output section. for information about how and when on-chip peripheral systems use these pins, refer to the appropriate section from table 2-1 . when an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin? output buffer. see the parallel input/output section for more details. pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. when the pta7?ta4 pins are controlled by the kbi module and are configured for rising-edge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. similarly, when irq is configured as the irq input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. table 2-1 pin sharing references port pins alternate function reference (1) notes : 1. see this section for information about modules that share these pins. pta7?ta0 kbi7?bi0 keyboard interrupt (kbi) module ptb7?tb0 ad7?d0 analog-to-digital converter (atd) module ptc7?tc4 parallel input/output ptc3?tc2 scl?da inter-integrated circuit (iic) module ptc1?tc0 rxd2?xd2 serial communications interface (sci) module ptd7?td3 tpm2ch4 tpm2ch0 timer/pwm (tpm) module ptd2?td0 tpm1ch2 tpm1ch0 timer/pwm (tpm) module pte7?te6 parallel input/output pte5 pte4 pte3 pte2 spsck miso mosi ss serial peripheral interface (spi) module pte1?te0 rxd1?xd1 serial communications interface (sci) module ptf7?tf0 parallel input/output ptg7?tg3 parallel input/output ptg2?tg1 extal?tal internal clock generator (icg) module ptg0 bkgd/ms development support
pins and connections mc9s08gb/gt 30 motorola 2.3.6 signal properties summary table 2-2 summarizes i/o pin characteristics. these characteristics are determined by the way the common pin interfaces are hardwired to internal circuits. table 2-2 signal properties pin name dir high current pin output slew (1) pull-up (2) comments v dd v ss v ddad v ssad v refh v refl reset i/o y n y pin contains integrated pullup. irq i y irqpe must be set to enable irq function. irq does not have a clamp diode to v dd . irq should not be driven above v dd . pullup/pulldown active when irq pin function enabled. pullup forced on when irq enabled for falling edges; pulldown forced on when irq enabled for rising edges. pta0/kbip0 i/o n swc swc pta1/kbip1 i/o n swc swc pta2/kbip2 i/o n swc swc pta3/kbip3 i/o n swc swc pta4/kbip4 i/o n swc swc pullup/pulldown active when kbi pin function enabled. pullup forced on when kbipx enabled for falling edges; pulldown forced on when kbipx enabled for rising edges. pta5/kbip5 i/o n swc swc pta6/kbip6 i/o n swc swc pta7/kbip7 i/o n swc swc ptb0/ad0 i/o n swc swc ptb1/ad1 i/o n swc swc ptb2/ad2 i/o n swc swc ptb3/ad3 i/o n swc swc ptb4/ad4 i/o n swc swc ptb5/ad5 i/o n swc swc ptb6/ad6 i/o n swc swc ptb7/ad7 i/o n swc swc ptc0/txd2 i/o y swc swc when pin is con?ured for sci function, pin is con?ured for partial output drive. ptc1/rxd2 i/o y swc swc ptc2/sda i/o y swc swc ptc3/scl i/o y swc swc ptc4 i/o y swc swc ptc5 i/o y swc swc not available on 42-pin pkg ptc6 i/o y swc swc not available on 42-pin pkg
data sheet ?mc9s08gb60/d v1.5 motorola 31 mc9s08gb/gt ptc7 i/o y swc swc not available on 42- or 44-pin pkg ptd0/tpm1ch0 i/o n swc swc ptd1/tpm1ch1 i/o n swc swc ptd2/tpm1ch2 i/o n swc swc not available on 42- or 44-pin pkg ptd3/tpm2ch0 i/o n swc swc ptd4/tpm2ch1 i/o n swc swc ptd5/tpm2ch2 i/o n swc swc not available on 42- or 44-pin pkg ptd6/tpm2ch3 i/o n swc swc not available on 42- or 44-pin pkg ptd7/tpm2ch4 i/o n swc swc not available on 42- or 44-pin pkg pte0/txd1 i/o n swc swc pte1/rxd1 i/o n swc swc pte2/ ss i/o n swc swc pte3/miso i/o n swc swc pte4/mosi i/o n swc swc pte5/spsck i/o n swc swc pte6 i/o n swc swc not available on 42- or 44-pin pkg pte7 i/o n swc swc not available on 42- or 44-pin pkg ptf0 i/o y swc swc not available on 42- or 44-pin pkg ptf1 i/o y swc swc not available on 42- or 44-pin pkg ptf2 i/o y swc swc not available on 42- or 44-pin pkg ptf3 i/o y swc swc not available on 42- or 44-pin pkg ptf4 i/o y swc swc not available on 42- or 44-pin pkg ptf5 i/o y swc swc not available on 42- or 44-pin pkg ptf6 i/o y swc swc not available on 42- or 44-pin pkg ptf7 i/o y swc swc not available on 42- or 44-pin pkg ptg0/bkgd/ms o n swc swc pullup enabled and slew rate disabled when bdm function enabled. ptg1/xtal i/o n swc swc pullup and slew rate disabled when xtal pin function. ptg2/extal i/o n swc swc pullup and slew rate disabled when extal pin function. ptg3 i/o n swc swc not available on 42- or 44-pin pkg ptg4 i/o n swc swc not available on 42- or 44-pin pkg ptg5 i/o n swc swc not available on 42- or 44-pin pkg ptg6 i/o n swc swc not available on 42- or 44-pin pkg ptg7 i/o n swc swc not available on 42- or 44-pin pkg notes : 1. swc is software controlled slew rate, the register is associated with the respective port. 2. swc is software controlled pullup resistor, the register is associated with the respective port. table 2-2 signal properties (continued) pin name dir high current pin output slew (1) pull-up (2) comments
pins and connections mc9s08gb/gt 32 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 33 mc9s08gb/gt section 3 modes of operation 3.1 introduction the operating modes of the mc9s08gb/gt are described in this section. entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 features active background mode for code development wait mode: cpu shuts down to conserve power system clocks running full voltage regulation maintained stop modes: system clocks stopped; voltage regulator in standby stop1 ?full power down of internal circuits for maximum power savings stop2 ?partial power down of internal circuits, ram contents retained stop3 ?all internal circuits powered for fast recovery 3.3 run mode this is the normal operating mode for the mc9s08gb/gt. this mode is selected when the bkgd/ms pin is high at the rising edge of reset. in this mode, the cpu executes code from internal memory with execution beginning at the address fetched from memory at $fffe:$ffff after reset. 3.4 active background mode the active background mode functions are managed through the background debug controller (bdc) in the hcs08 core. the bdc, together with the on-chip debug module (dbg), provide the means for analyzing mcu operation during software development. active background mode is entered in any of five ways: when the bkgd/ms pin is low at the rising edge of reset when a background command is received through the bkgd pin when a bgnd instruction is executed when encountering a bdc breakpoint when encountering a dbg breakpoint
modes of operation mc9s08gb/gt 34 motorola once in active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructions from the user? application program. background commands are of two types: non-intrusive commands, defined as commands that can be issued while the user program is running. non-intrusive commands can be issued through the bkgd pin while the mcu is in run mode; non-intrusive commands can also be executed when the mcu is in the active background mode. non-intrusive commands include: memory access commands memory-access-with-status commands bdc register access commands the background command active background commands, which can only be executed while the mcu is in active background mode. active background commands include commands to: read or write cpu registers trace one user program instruction at a time leave active background mode to return to the user? application program (go) the active background mode is used to program a bootloader or user application program into the flash program memory before the mcu is operated in run mode for the first time. when the mc9s08gb/gt is shipped from the motorola factory, the flash program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the flash memory is initially programmed. the active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. for additional information about the active background mode, refer to the development support section. 3.5 wait mode wait mode is entered by executing a wait instruction. upon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background command and memory-access-with-status commands are available when the mcu is in wait mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode.
data sheet ?mc9s08gb60/d v1.5 motorola 35 mc9s08gb/gt 3.6 stop modes one of three stop modes is entered upon execution of a stop instruction when the stope bit in the system option register is set. in all stop modes, all internal clocks are halted. if the stope bit is not set when the cpu executes a stop instruction, the mcu will not enter any of the stop modes and an illegal opcode reset is forced. the stop modes are selected by setting the appropriate bits in spmsc2. table 3-1 summarizes the behavior of the mcu in each of the stop modes. 3.6.1 stop1 mode the stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the mcu to be powered down. to select entry into stop1 mode upon execution of a stop instruction, the user must set the pdc bit in spmsc2 and clear the ppdc bit in spmsc2. when the mcu is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned off. the voltage regulator is in a low-power standby state, as is the atd. exit from stop1 is done by asserting either of the wake-up pins on the mcu: reset or irq. irq is always an active low input when the mcu is in stop1, regardless of how it was configured before entering stop1. entering stop1 mode automatically asserts lvd. stop1 cannot be exited until v dd >v lvdh/l rising (v dd must rise above the lvi rearm voltage). upon wake-up from stop1 mode, the mcu will start up as from a power-on reset (por). the cpu will take the reset vector. 3.6.2 stop2 mode the stop2 mode provides very low standby power consumption and maintains the contents of ram and the current state of all of the i/o pins. to select entry into stop2 upon execution of a stop instruction, the user must execute a stop instruction while the ppdc and pdc bits in spmsc2 are set. table 3-1 stop mode behavior mode pdc ppdc cpu, digital peripherals, flash ram icg atd regulator i/o pins rti stop1 1 0 off off off disabled (1) notes : 1. either atd stop mode or power-down mode depending on the state of atdpu. off reset off stop2 1 1 off standby off disabled standby states held optionally on stop3 0 don? care standby standby off (2) 2. crystal oscillator can be configured to run in stop3. please see the icg registers. disabled standby states held optionally on
modes of operation mc9s08gb/gt 36 motorola before entering stop2 mode, the user must save the contents of the i/o port registers, as well as any other memory-mapped registers which they want to restore after exit of stop2, to locations in ram. upon exit of stop2, these values can be restored by user software before pin latches are opened. when the mcu is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the ram. the voltage regulator is in a low-power standby state, as is the atd. upon entry into stop2, the states of the i/o pins are latched. the states are held while in stop2 mode and after exiting stop2 mode until a logic 1 is written to ppdack in spmsc2. exit from stop2 is done by asserting either of the wake-up pins: reset or irq, or by an rti interrupt. irq is always an active low input when the mcu is in stop2, regardless of how it was configured before entering stop2. upon wake-up from stop2 mode, the mcu will start up as from a power-on reset (por) except pin states remain latched. the cpu will take the reset vector. the system and all peripherals will be in their default reset states and must be initialized. after waking up from stop2, the ppdf bit in spmsc2 is set. this flag may be used to direct user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latched until a logic 1 is written to ppdack in spmsc2. to maintain i/o state for pins that were configured as general-purpose i/o, the user must restore the contents of the i/o port registers, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restored from ram before writing to ppdack, then the register bits will assume their reset states when the i/o pin latches are opened and the i/o pins will switch to their reset states. for pins that were configured as peripheral i/o, the user must reconfigure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.6.3 stop3 mode upon entering the stop3 mode, all of the clocks in the mcu, including the oscillator itself, are halted. the icg is turned off, the atd is disabled, and the voltage regulator is put in standby. the states of all of the internal registers and logic, as well as the ram content, are maintained. the i/o pin states are not latched at the pin as in stop2. instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. exit from stop3 is done by asserting reset, an asynchronous interrupt pin, or through the real-time interrupt. the asynchronous interrupt pins are the irq or kbi pins. if stop3 is exited by means of the reset pin, then the mcu will be reset and operation will resume after taking the reset vector. exit by means of an asynchronous interrupt or the real-time interrupt will result in the mcu taking the appropriate interrupt vector. a separate self-clocked source ( 1 khz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. when rtis2:rtis1:rtis0 = 0:0:0, the real-time interrupt function
data sheet ?mc9s08gb60/d v1.5 motorola 37 mc9s08gb/gt and this 1-khz source are disabled. power consumption is lower when the 1-khz source is disabled, but in that case the real-time interrupt cannot wake the mcu from stop. 3.6.4 active bdm enabled in stop mode entry into the active background mode from run mode is enabled if the enbdm bit in bdcscr is set. this register is described in the development support section of this data sheet. if enbdm is set when the cpu executes a stop instruction, the system clocks to the background debug logic remain active when the mcu enters stop mode so background debug communication is still possible. in addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. if the user attempts to enter either stop1 or stop2 with enbdm set, the mcu will instead enter stop3. most background commands are not available in stop mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. once in background debug mode, all background commands are available. the table below summarizes the behavior of the mcu in stop when entry into the background debug mode is enabled. 3.6.5 lvd enabled in stop mode the lvd system is capable of generating either an interrupt or a reset when the supply voltage drops below the lvd voltage. if the lvd is enabled in stop by setting the lvde and the lvdse bits in spmsc1 when the cpu executes a stop instruction, then the voltage regulator remains active during stop mode. if the user attempts to enter either stop1 or stop2 with the lvd enabled for stop (lvdse = 1), the mcu will instead enter stop3. the table below summarizes the behavior of the mcu in stop when the lvd is enabled. table 3-2 bdm enabled stop mode behavior mode pdc ppdc cpu, digital peripherals, flash ram icg atd regulator i/o pins rti stop3 don? care don? care standby standby active disabled (1) notes : 1. either atd stop mode or power-down mode depending on the state of atdpu. active states held optionally on table 3-3 lvd enabled stop mode behavior mode pdc ppdc cpu, digital peripherals, flash ram icg atd regulator i/o pins rti stop3 don? care don? care standby standby standby disabled (1) notes : 1. either atd stop mode or power-down mode depending on the state of atdpu. active states held optionally on
modes of operation mc9s08gb/gt 38 motorola 3.6.6 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal peripheral modules are stopped. even in the exception case (enbdm = 1), where clocks are kept alive to the background debug logic, clocks to the peripheral systems are halted to reduce power consumption. refer to 3.6.1 stop1 mode , 3.6.2 stop2 mode , and 3.6.3 stop3 mode for specific information on system behavior in stop modes. i/o pins all i/o pin states remain unchanged when the mcu enters stop3 mode. if the mcu is configured to go into stop2 mode, all i/o pins states are latched before entering stop. if the mcu is configured to go into stop1 mode, all i/o pins are forced to their default reset state upon entry into stop. memory all ram and register contents are preserved while the mcu is in stop3 mode. all registers will be reset upon wake-up from stop2, but the contents of ram are preserved and pin states remain latched until the ppdack bit is written. the user may save any memory-mapped register data into ram before entering stop2 and restore the data upon exit from stop2. all registers will be reset upon wake-up from stop1 and the contents of ram are not preserved. the mcu must be initialized as upon reset. the contents of the flash memory are non-volatile and are preserved in any of the stop modes. icg ?in stop3 mode, the icg enters its low-power standby state. either the oscillator or the internal reference may be kept running when the icg is in standby by setting the appropriate control bit. in both stop2 and stop1 modes, the icg is turned off. neither the oscillator nor the internal reference can be kept running in stop2 or stop1, even if enabled within the icg module. tpm when the mcu enters stop mode, the clock to the tpm1 and tpm2 modules stop. the modules halt operation. if the mcu is configured to go into stop2 or stop1 mode, the tpm modules will be reset upon wake-up from stop and must be reinitialized. atd when the mcu enters stop mode, the atd will enter a low-power standby state . no conversion operation will occur while in stop. if the mcu is configured to go into stop2 or stop1 mode, the atd will be reset upon wake-up from stop and must be reinitialized. kbi ?during stop3, the kbi pins that are enabled continue to function as interrupt sources that are capable of waking the mcu from stop3. the kbi is disabled in stop1 and stop2 and must be reinitialized after waking up from either of these modes. sci ?when the mcu enters stop mode, the clocks to the sci1 and sci2 modules stop. the modules halt operation. if the mcu is configured to go into stop2 or stop1 mode, the sci modules will be reset upon wake-up from stop and must be reinitialized. spi when the mcu enters stop mode, the clocks to the spi module stop. the module halts operation. if the mcu is configured to go into stop2 or stop1 mode, the spi module will be reset upon wake-up from stop and must be reinitialized.
data sheet ?mc9s08gb60/d v1.5 motorola 39 mc9s08gb/gt iic when the mcu enters stop mode, the clocks to the iic module stops. the module halts operation. if the mcu is configured to go into stop2 or stop1 mode, the iic module will be reset upon wake-up from stop and must be reinitialized. voltage regulator the voltage regulator enters a low-power standby state when the mcu enters any of the stop modes unless the lvd is enabled in stop mode or bdm is enabled.
modes of operation mc9s08gb/gt 40 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 41 mc9s08gb/gt section 4 memory 4.1 mc9s08gb/gt memory map as shown in figure 4-1 , on-chip memory in the mc9s08gb/gt series of mcus consists of ram, flash program memory for nonvolatile data storage, plus i/o and control/status registers. the registers are divided into three groups: direct-page registers ($0000 through $007f) high-page registers ($1800 through $182b) nonvolatile registers ($ffb0 through $ffbf) figure 4-1 mc9s08gb/gt memory map direct page registers ram flash high page registers flash 4096 bytes 1920 bytes 59348 bytes $0000 $007f $0080 $107f $1800 $17ff $182b $182c $ffff $1080 direct page registers ram high page registers flash 32768 bytes $0000 $007f $0080 $087f $1800 $17ff $182b $182c $ffff $0880 2048 bytes unimplemented 26580 bytes unimplemented 3968 bytes $8000 $7fff mc9s08gb/gt60 mc9s08gb/gt32
memory mc9s08gb/gt 42 motorola 4.1.1 reset and interrupt vector assignments table 4-1 shows address assignments for reset and interrupt vectors. the vector names shown in this table are the labels used in the motorola-provided equate file for the mc9s08gb/gt. for more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to the resets, interrupts, and system configuration section. table 4-1 reset and interrupt vectors address (high/low) vector vector name $ffc0:ffc1 $ffca:ffcb unused vector space (available for user program) $ffcc:ffcd rti vrti $ffce:ffcf iic viic $ffd0:ffd1 atd conversion vatd $ffd2:ffd3 keyboard vkeyboard $ffd4:ffd5 sci2 transmit vsci2tx $ffd6:ffd7 sci2 receive vsci2rx $ffd8:ffd9 sci2 error vsci2err $ffda:ffdb sci1 transmit vsci1tx $ffdc:ffdd sci1 receive vsci1rx $ffde:ffdf sci1 error vsci1err $ffe0:ffe1 spi vspi $ffe2:ffe3 tpm2 over?w vtpm2ovf $ffe4:ffe5 tpm2 channel 4 vtpm2ch4 $ffe6:ffe7 tpm2 channel 3 vtpm2ch3 $ffe8:ffe9 tpm2 channel 2 vtpm2ch2 $ffea:ffeb tpm2 channel 1 vtpm2ch1 $ffec:ffed tpm2 channel 0 vtpm2ch0 $ffee:ffef tpm1 over?w vtpm1ovf $fff0:fff1 tpm1 channel 2 vtpm1ch2 $fff2:fff3 tpm1 channel 1 vtpm1ch1 $fff4:fff5 tpm1 channel 0 vtpm1ch0 $fff6:fff7 icg vicg $fff8:fff9 low voltage detect vlvd $fffa:fffb irq virq $fffc:fffd swi vswi $fffe:ffff reset vreset
data sheet ?mc9s08gb60/d v1.5 motorola 43 mc9s08gb/gt 4.2 register addresses and bit assignments the registers in the mc9s08gb/gt are divided into these three groups: direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. high-page registers are used much less often, so they are located above $1800 in the memory map. this leaves more room in the direct page for more frequently used registers and variables. the nonvolatile register area consists of a block of 16 locations in flash memory at $ffb0?ffbf. nonvolatile register locations include: three values which are loaded into working registers at reset an 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory since the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. direct-page registers can be accessed with efficient direct addressing mode instructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page registers and control bits. the direct page registers in table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. because of this, the lower byte of the address in column one is shown in bold text. in table 4-3 and table 4-4 the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-4 , the register names in column two are shown in bold to set them apart from the bit names to the right. cells that are not associated with named bits are shaded. a shaded cell with a 0 indicates this unused bit always reads as a 0. shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
memory mc9s08gb/gt 44 motorola table 4-2 direct-page register summary address register name bit 7 654321 bit 0 $00 00 ptad ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 $00 01 ptape ptape7 ptape6 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 $00 02 ptase ptase7 ptase6 ptase5 ptase4 ptase3 ptase2 ptase1 ptase0 $00 03 ptadd ptadd7 ptadd6 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 $00 04 ptbd ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 $00 05 ptbpe ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 $00 06 ptbse ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 $00 07 ptbdd ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 $00 08 ptcd ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 $00 09 ptcpe ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 $00 0a ptcse ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 $00 0b ptcdd ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 $00 0c ptdd ptdd7 ptdd6 ptdd5 ptdd4 ptdd3 ptdd2 ptdd1 ptdd0 $00 0d ptdpe ptdpe7 ptdpe6 ptdpe5 ptdpe4 ptdpe3 ptdpe2 ptdpe1 ptdpe0 $00 0e ptdse ptdse7 ptdse6 ptdse5 ptdse4 ptdse3 ptdse2 ptdse1 ptdse0 $00 0f ptddd ptddd7 ptddd6 ptddd5 ptddd4 ptddd3 ptddd2 ptddd1 ptddd0 $00 10 pted pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 $00 11 ptepe ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 $00 12 ptese ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 $00 13 ptedd ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 $00 14 irqsc 0 0 irqedg irqpe irqf irqack irqie irqmod $00 15 reserved $00 16 kbisc kbedg7 kbedg6 kbedg5 kbedg4 kbf kback kbie kbimod $00 17 kbipe kbipe7 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 $00 18 sci1bdh 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 $00 19 sci1bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 $00 1a sci1c1 loops sciswai rsrc m wake ilt pe pt $00 1b sci1c2 tie tcie rie ilie te re rwu sbk $00 1c sci1s1 tdre tc rdrf idle or nf fe pf $00 1d sci1s2 0 0 0 0 0 0 0 raf $00 1e sci1c3 r8 t8 txdir 0 orie neie feie peie $00 1f sci1d bit 7 654321 bit 0 $00 20 sci2bdh 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 $00 21 sci2bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 $00 22 sci2c1 loops sciswai rsrc m wake ilt pe pt $00 23 sci2c2 tie tcie rie ilie te re rwu sbk $00 24 sci2s1 tdre tc rdrf idle or nf fe pf $00 25 sci2s2 0 0 0 0 0 0 0 raf $00 26 sci2c3 r8 t8 txdir 0 orie neie feie peie $00 27 sci2d bit 7 654321 bit 0
data sheet ?mc9s08gb60/d v1.5 motorola 45 mc9s08gb/gt $00 28 spic1 spie spe sptie mstr cpol cpha ssoe lsbfe $00 29 spic2 0 0 0 modfen bidiroe 0 spiswai spc0 $00 2a spibr 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 $00 2b spis sprf 0 sptef modf 0 0 0 0 $00 2c reserved 0 0 0 0 0 0 0 0 $00 2d spid bit 7 654321 bit 0 $00 2e reserved 0 0 0 0 0 0 0 0 $00 2f reserved 0 0 0 0 0 0 0 0 $00 30 tpm1sc tof toie cpwms clksb clksa ps2 ps1 ps0 $00 31 tpm1cnth bit 15 14 13 12 11 10 9 bit 8 $00 32 tpm1cntl bit 7 654321 bit 0 $00 33 tpm1modh bit 15 14 13 12 11 10 9 bit 8 $00 34 tpm1modl bit 7 654321 bit 0 $00 35 tpm1c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 $00 36 tpm1c0vh bit 15 14 13 12 11 10 9 bit 8 $00 37 tpm1c0vl bit 7 654321 bit 0 $00 38 tpm1c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 $00 39 tpm1c1vh bit 15 14 13 12 11 10 9 bit 8 $00 3a tpm1c1vl bit 7 654321 bit 0 $00 3b tpm1c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 $00 3c tpm1c2vh bit 15 14 13 12 11 10 9 bit 8 $00 3d tpm1c2vl bit 7 654321 bit 0 $00 3e $00 3f reserved $00 40 ptfd ptfd7 ptfd6 ptfd5 ptfd4 ptfd3 ptfd2 ptfd1 ptfd0 $00 41 ptfpe ptfpe7 ptfpe6 ptfpe5 ptfpe4 ptfpe3 ptfpe2 ptfpe1 ptfpe0 $00 42 ptfse ptfse7 ptfse6 ptfse5 ptfse4 ptfse3 ptfse2 ptfse1 ptfse0 $00 43 ptfdd ptfdd7 ptfdd6 ptfdd5 ptfdd4 ptfdd3 ptfdd2 ptfdd1 ptfdd0 $00 44 ptgd ptgd7 ptgd6 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 $00 45 ptgpe ptgpe7 ptgpe6 ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 $00 46 ptgse ptgse7 ptgse6 ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 $00 47 ptgdd ptgdd7 ptgdd6 ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 $00 48 icgc1 0 range refs clks oscsten 0* 0 $00 49 icgc2 lolre mfd locre rfd $00 4a icgs1 clkst refst lols lock locs ercs icgif $00 4b icgs2 0 0 0 0 0 0 0 dcos $00 4c icgfltu 0 0 0 0 flt $00 4d icgfltl flt $00 4e icgtrm trim $00 4f reserved 0 0 0 0 0 0 0 0 * this bit is reserved for motorola internal use only. always write a 0 to this bit. table 4-2 direct-page register summary (continued) address register name bit 7 654321 bit 0
memory mc9s08gb/gt 46 motorola $00 50 atdc atdpu djm res8 sgn prs $00 51 atdsc ccf atdie atdco atdch $00 52 atdrh bit 7 654321 bit 0 $00 53 atdrl bit 7 654321 bit 0 $00 54 atdpe atdpe7 atdpe6 atdpe5 atdpe4 atdpe3 atdpe2 atdpe1 atdpe0 $00 55 $00 57 reserved $00 58 iica addr 0 $00 59 iicf mult icr $00 5a iicc iicen iicie mst tx txak rsta 0 0 $00 5b iics tcf iaas busy arbl 0 srw iicif rxak $00 5c iicd data $00 5d $00 5f reserved $00 60 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 $00 61 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 $00 62 tpm2cntl bit 7 654321 bit 0 $00 63 tpm2modh bit 15 14 13 12 11 10 9 bit 8 $00 64 tpm2modl bit 7 654321 bit 0 $00 65 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 $00 66 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 $00 67 tpm2c0vl bit 7 654321 bit 0 $00 68 tpm2c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 $00 69 tpm2c1vh bit 15 14 13 12 11 10 9 bit 8 $00 6a tpm2c1vl bit 7 654321 bit 0 $00 6b tpm2c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 $00 6c tpm2c2vh bit 15 14 13 12 11 10 9 bit 8 $00 6d tpm2c2vl bit 7 654321 bit 0 $00 6e tpm2c3sc ch3f ch3ie ms3b ms3a els3b els3a 0 0 $00 6f tpm2c3vh bit 15 14 13 12 11 10 9 bit 8 $00 70 tpm2c3vl bit 7 654321 bit 0 $00 71 tpm2c4sc ch4f ch4ie ms4b ms4a els4b els4a 0 0 $00 72 tpm2c4vh bit 15 14 13 12 11 10 9 bit 8 $00 73 tpm2c4vl bit 7 654321 bit 0 $00 74 $00 7f reserved table 4-2 direct-page register summary (continued) address register name bit 7 654321 bit 0
data sheet ?mc9s08gb60/d v1.5 motorola 47 mc9s08gb/gt high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the direct addressable memory space, starting at $1800. table 4-3 high-page register summary address register name bit 7 654321 bit 0 $1800 srs por pin cop ilop 0 icg lvd 0 $1801 sbdfr 0 0 0 0 0 0 0 bdfr $1802 sopt cope copt stope 0 0 bkgdpe $1803 $1805 reserved $1806 sdidh rev3 rev2 rev1 rev0 id11 id10 id9 id8 $1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 $1808 srtisc rtif rtiack rticlks rtie 0 rtis2 rtis1 rtis0 $1809 spmsc1 lvdf lvdack lvdie lvdre lvdse lvde 0 0 $180a spmsc2 lvwf lvwack lvdv lvwv ppdf ppdack pdc ppdc $180b $180f reserved $1810 dbgcah bit 15 14 13 12 11 10 9 bit 8 $1811 dbgcal bit 7 654321 bit 0 $1812 dbgcbh bit 15 14 13 12 11 10 9 bit 8 $1813 dbgcbl bit 7 654321 bit 0 $1814 dbgfh bit 15 14 13 12 11 10 9 bit 8 $1815 dbgfl bit 7 654321 bit 0 $1816 dbgc dbgen arm tag brken rwa rwaen rwb rwben $1817 dbgt trgsel begin 0 0 trg3 trg2 trg1 trg0 $1818 dbgs af bf armf 0 cnt3 cnt2 cnt1 cnt0 $1819 $181f reserved $1820 fcdiv divld prdiv8 div5 div4 div3 div2 div1 div0 $1821 fopt keyen fnored 0 0 0 0 sec01 sec00 $1822 reserved $1823 fcnfg 0 0 keyacc 0 0 0 0 0 $1824 fprot fpopen fpdis fps2 fps1 fps0 0 0 0 $1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 $1826 fcmd fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 $1827 $182b reserved
memory mc9s08gb/gt 48 motorola nonvolatile flash registers, shown in table 4-4 , are located in the flash memory. these registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. during reset events, the contents of nvprot and nvopt in the nonvolatile register area of the flash memory are transferred into corresponding fprot and fopt working registers in the high-page registers to control security and block protection options. provided the key enable (keyen) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. this key mechanism can be accessed only through user code running in secure memory. (a security key cannot be entered directly through background debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if the security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally through the background debug interface) and verifying that flash is blank. to avoid returning to secure mode after the next reset, program the security bits (sec01:sec00) to the unsecured state (1:0). 4.3 ram the mc9s08gb/gt includes static ram. the locations in ram below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed program variables in this area of ram is preferred. the ram retains data when the mcu is in low-power wait, stop2, or stop3 mode. at power-on or after wakeup from stop1, the contents of ram are uninitialized. ram data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for ram retention. for compatibility with older m68hc05 mcus, the hcs08 resets the stack pointer to $00ff. in the mc9s08gb/gt, it is usually best to reinitialize the stack pointer to the top of the ram so the direct page ram can be used for frequently accessed ram variables and bit-addressable program variables. include the following 2-instruction sequence in your reset initialization routine (where ramlast is equated to the highest address of the ram in the motorola-provided equate file). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) table 4-4 nonvolatile register summary address register name bit 7 654321 bit 0 $ffb0 $ffb7 nvbackkey 8-byte comparison key $ffb8 $ffbc reserved $ffbd nvprot fpopen fpdis fps2 fps1 fps0 0 0 0 $ffbe reserved (1) notes : 1. this location can be used to store the factory trim value for the icg. $ffbf nvopt keyen fnored 0 0 0 0 sec01 sec00
data sheet ?mc9s08gb60/d v1.5 motorola 49 mc9s08gb/gt when security is enabled, the ram is considered a secure memory resource and is not accessible through bdm or through code executing from non-secure memory. see section 4.5 security for a detailed description of the security feature. 4.4 flash the flash memory is intended primarily for program storage. in-circuit programming allows the operating program to be loaded into the flash memory after final assembly of the application product. it is possible to program the entire array through the single-wire background debug interface. because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths. for a more detailed discussion of in-circuit and in-application programming, refer to the hcs08 family reference manual, volume i, motorola document order number hcs08rmv1/d. 4.4.1 features features of the flash memory include: flash size mc9s08gb/gt60 ?61268 bytes (120 pages of 512 bytes each) mc9s08gb/gt32 ?32768 bytes (64 pages of 512 bytes each) single power supply program and erase command interface for fast program and erase operation up to 100,000 program/erase cycles at typical voltage and temperature flexible block protection security feature for flash and ram auto power-down for low-frequency read accesses 4.4.2 program and erase times before any program or erase command can be accepted, the flash clock divider register (fcdiv) must be written to set the internal clock for the flash module to a frequency (f fclk ) between 150 khz and 200 khz (see 4.6.1 flash clock divider register (fcdiv) ). this register can be written only once, so normally this write is done during reset initialization. fcdiv cannot be written if the access error flag, faccerr in fstat, is set. the user must ensure that faccerr is not set before writing to the fcdiv register. one period of the resulting clock (1/f fclk ) is used by the command processor to time program and erase pulses. an integer number of these timing pulses are used by the command processor to complete a program or erase command.
memory mc9s08gb/gt 50 motorola table 4-5 shows program and erase times. the bus clock frequency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk = 1/f fclk . the times are shown as a number of cycles of fclk and as an absolute time for the case where t fclk =5 s. program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages. 4.4.3 program and erase command execution the steps for executing any of the commands are listed below. the fcdiv register must be initialized and any error flags cleared before beginning command execution. the command execution steps are: 1. write a data value to an address in the flash array. the address and data information from this write is latched into the flash interface. this write is a required first step in any command sequence. for erase and blank check commands, the value of the data is not important. for page erase commands, the address may be any address in the 512-byte page of flash to be erased. for mass erase and blank check commands, the address can be any address in the flash memory. whole pages of 512 bytes are the smallest block of flash that may be erased. in the 60k version, there are two instances where the size of a block that is accessible to the user is less than 512 bytes: the first page following ram, and the first page following the high page registers. these pages are overlapped by the ram and high page registers respectively. 2. write the command code for the desired command to fcmd. the five valid commands are blank check ($05), byte program ($20), burst program ($25), page erase ($40), and mass erase ($41). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launches the complete command. aborting a command in this way sets the faccerr access error flag which must be cleared before starting a new command. table 4-5 program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s byte program (burst) 4 20 s (1) notes : 1. excluding start/end overhead page erase 4000 20 ms mass erase 20,000 100 ms
data sheet ?mc9s08gb60/d v1.5 motorola 51 mc9s08gb/gt a strictly monitored procedure must be followed or the command will not be accepted. this minimizes the possibility of any unintended changes to the flash memory contents. the command complete flag (fccf) indicates when a command is complete. the command sequence must be completed by clearing fcbef to launch the command. figure 4-2 below is a flowchart for executing all of the commands except for burst programming. the fcdiv register must be initialized before using any flash commands. this only must be done once following a reset. figure 4-2 flash program and erase flowchart start write to flash to buffer address and data write command to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (2) 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) only required once after reset.
memory mc9s08gb/gt 52 motorola 4.4.4 burst program execution the burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. this is possible because the high voltage to the flash array does not need to be disabled between program operations. ordinarily, when a program or erase command is issued, an internal charge pump associated with the flash memory must be enabled to supply high voltage to the array. upon completion of the command, the charge pump is turned off. when a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if the following two conditions are met: 1. the next burst program command has been queued before the current program operation has completed. 2. the next sequential address selects a byte on the same physical row as the current byte being programmed. a row of flash memory consists of 64 bytes. a byte within a row is selected by addresses a5 through a0. a new row begins when addresses a5 through a0 are all zero. the first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. subsequent bytes will program in the burst program time provided that the conditions above are met. in the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array.
data sheet ?mc9s08gb60/d v1.5 motorola 53 mc9s08gb/gt figure 4-3 flash burst program flowchart 1 0 fcbef ? start write to flash to buffer address and data write command to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (2) no yes new burst command ? 1 0 fccf ? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 1 0 faccerr ? clear error faccerr ? write to fcdiv (1) (1) only required once after reset.
memory mc9s08gb/gt 54 motorola 4.4.5 access errors an access error occurs whenever the command execution protocol is violated. any of the following specific actions will cause the access error flag (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to faccerr in fstat before any command can be processed. writing to a flash address before the internal flash clock frequency has been set by writing to the fcdiv register writing to a flash address while fcbef is not set (a new command cannot be started until the command buffer is empty.) writing a second time to a flash address before launching the previous command (there is only one write to flash for every command.) writing a second time to fcmd before launching the previous command (there is only one write to fcmd for every command.) writing to any flash control register other than fcmd after writing to a flash address writing any command code other than the five allowed codes ($05, $20, $25, $40, or $41) to fcmd accessing (read or write) any flash control register other than the write to fstat (to clear fcbef and launch the command) after writing the command to fcmd. the mcu enters stop mode while a program or erase command is in progress (the command is aborted.) writing the byte program, burst program, or page erase command code ($20, $25, or $40) with a background debug command while the mcu is secured (the background debug controller can only do blank check and mass erase commands when the mcu is secure.) writing 0 to fcbef to cancel a partial command 4.4.6 flash block protection block protection prevents program or erase changes for flash memory locations in a designated address range. mass erase is disabled when any block of flash is protected. the mc9s08gb/gt allows a block of memory at the end of flash, and/or the entire flash memory to be block protected. a disable control bit and a 3-bit control field, allows the user to set the size of this block. a separate control bit allows block protection of the entire flash memory array. all seven of these control bits are located in the fprot register (see 4.6.4 flash protection register (fprot and nvprot) ). at reset, the high-page register (fprot) is loaded with the contents of the nvprot location which is in the nonvolatile register block of the flash memory. the value in fprot cannot be changed directly from application software so a runaway program cannot alter the block protection settings. if the last 512 bytes of flash which includes the nvprot register is protected, the application program cannot alter the block protection settings (intentionally or unintentionally). the fprot control bits can be written by background debug commands to allow a way to erase a protected flash memory.
data sheet ?mc9s08gb60/d v1.5 motorola 55 mc9s08gb/gt one use for block protection is to block protect an area of flash memory for a bootloader program. this bootloader program then can be used to erase the rest of the flash memory and reprogram it. since the bootloader is protected, it remains intact even if mcu power is lost in the middle of an erase and reprogram operation. 4.4.7 vector redirection whenever any block protection is enabled, the reset and interrupt vectors will be protected. vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. vector redirection is enabled by programming the fnored bit in the nvopt register located at address $ffbf to zero. for redirection to occur, at least some portion but not all of the flash memory must be block protected by programming the nvprot register located at address $ffbd. all of the interrupt vectors (memory locations $ffc0?fffd) are redirected, while the reset vector ($fffe:ffff) is not. for example, if 512 bytes of flash are protected, the protected address region is from $fe00 through $ffff. the interrupt vectors ($ffc0?fffd) are redirected to the locations $fdc0?fdfd. now, if an spi interrupt is taken for instance, the values in the locations $fde0:fde1 are used for the vector instead of the values in the locations $ffe0:ffe1. this allows the user to reprogram the unprotected portion of the flash with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.5 security the mc9s08gb/gt includes circuitry to prevent unauthorized access to the contents of flash and ram memory. when security is engaged, flash and ram are considered secure resources. direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. programs executing within secure memory have normal access to any mcu memory locations and resources. attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s). security is engaged or disengaged based on the state of two nonvolatile register bits (sec01:sec00) in the fopt register. during reset, the contents of the nonvolatile location nvopt are copied from flash into the working fopt register in high-page register space. a user engages security by programming the nvopt location which can be done at the same time the flash memory is programmed. the 1:0 state disengages security while the other three combinations engage security. notice the erased state (1:1) makes the mcu secure. during development, whenever the flash is erased, it is good practice to immediately program the sec00 bit to 0 in nvopt so sec01:sec00 = 1:0. this would allow the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can still be used for background memory access commands, but the mcu cannot enter active background mode except by holding bkgd/ms low at the rising edge of reset. a user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile keyen bit in nvopt/fopt is 0, the backdoor key is disabled and there
memory mc9s08gb/gt 56 motorola is no way to disengage security without completely erasing all flash locations. if keyen is 1, a secure user program can temporarily disengage security by: 1. writing 1 to keyacc in the fcnfg register. this makes the flash module interpret writes to the backdoor comparison key locations (nvbackkey through nvbackkey+7) as values to be compared against the key rather than as the first step in a flash program or erase command. 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be done in order starting with the value for nvbackkey and ending with nvbackkey+7. sthx should not be used for these writes because these writes cannot be done on adjacent bus cycles. user software normally would get the key codes from outside the mcu system through a communication interface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was just written matches the key stored in the flash locations, sec01:sec00 are automatically changed to 1:0 and security will be disengaged until the next reset. the security key can be written only from ram, so it cannot be entered through background commands without the cooperation of a secure user program. the flash memory cannot be accessed by read operations while keyacc is set. the backdoor comparison key (nvbackkey through nvbackkey+7) is located in flash memory locations in the nonvolatile register space so users can program these locations just as they would program any other flash memory location. the nonvolatile registers are in the same 512-byte block of flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through the background debug interface by following these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash if necessary. 3. blank check flash. provided flash is completely erased, security is disengaged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec01:sec00 = 1:0. 4.6 flash registers and control bits the flash module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in flash memory which are copied into three corresponding high-page control registers at reset. there is also an 8-byte comparison key in flash memory. refer to table 4-3 and table 4-4 for the absolute address assignments for all flash registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file normally is used to translate these names into the appropriate absolute addresses.
data sheet ?mc9s08gb60/d v1.5 motorola 57 mc9s08gb/gt 4.6.1 flash clock divider register (fcdiv) bit 7 of this register is a read-only status flag. bits 6 through 0 may be read at any time but can be written only one time. before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. divld divisor loaded status flag when set, this read-only status flag indicates that the fcdiv register has been written since reset. reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 1 = fcdiv has been written since reset; erase and program operations enabled for flash. 0 = fcdiv has not been written since reset; erase and program operations disabled for flash. prdiv8 prescale (divide) flash clock by 8 1 = clock input to the flash clock divider is the bus rate clock divided by 8. 0 = clock input to the flash clock divider is the bus rate clock. div5:div0 divisor for flash clock divider the flash clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div5:div0 field plus one. the resulting frequency of the internal flash clock must fall within the range of 200 khz to 150 khz for proper flash operations. program/erase timing pulses are one cycle of this internal flash clock which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer number of these pulses to complete an erase or program operation. equation 1 if prdiv8 = 0 ?f fclk = f bus ([div5:div0] + 1) equation 2 if prdiv8 = 1 ?f fclk = f bus (8 ([div5:div0] + 1)) table 4-6 shows the appropriate values for prdiv8 and div5:div0 for selected bus frequencies. bit 7 6 54321 bit 0 read: divld prdiv8 div5 div4 div3 div2 div1 div0 write: reset: 0 0 000000 = unimplemented or reserved figure 4-4 flash clock divider register (fcdiv)
memory mc9s08gb/gt 58 motorola 4.6.2 flash options register (fopt and nvopt) during reset, the contents of the nonvolatile location nvopt are copied from flash into fopt. bits 5 through 2 are not used and always read 0. this register may be read at any time, but writes have no meaning or effect. to change the value in this register, erase and reprogram the nvopt location in flash memory as usual and then issue a new mcu reset. keyen backdoor key mechanism enable when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) firmware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to 4.5 security . 1 = if user firmware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7 in that order), security is temporarily disengaged until the next mcu reset. 0 = no backdoor key access allowed. fnored vector redirection disable when this bit is 1, then vector redirection is disabled. 1 = vector redirection disabled. 0 = vector redirection enabled. table 4-6 flash clock divider settings f bus prdiv8 (binary) div5:div0 (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 20 mhz 1 12 192.3 khz 5.2 s 10 mhz 0 49 200 khz 5 s 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s bit 7 6 54321 bit 0 read: keyen fnored 0000 sec01 sec00 write: reset: this register is loaded from nonvolatile location nvopt during reset. = unimplemented or reserved figure 4-5 flash options register (fopt)
data sheet ?mc9s08gb60/d v1.5 motorola 59 mc9s08gb/gt sec01:sec00 security state code this 2-bit field determines the security state of the mcu as shown in table 4-7 . when the mcu is secure, the contents of ram and flash memory cannot be accessed by instructions from any unsecured source including the background debug interface. for more detailed information about security, refer to 4.5 security . sec01:sec00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. 4.6.3 flash configuration register (fcnfg) bits 7 through 5 may be read or written at any time. bits 4 through 0 always read 0 and cannot be written. keyacc enable writing of access key this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to 4.5 security . 1 = writes to nvbackkey ($ffb0?ffb7) are interpreted as comparison key writes. reads of the flash return invalid data. 0 = writes to $ffb0?ffb7 are interpreted as the start of a flash programming or erase command. 4.6.4 flash protection register (fprot and nvprot) during reset, the contents of the nonvolatile location nvprot is copied from flash into fprot. bits 0, 1, and 2 are not used and each always reads as 0. this register may be read at any time, but user program writes have no meaning or effect. background debug commands can write to fprot. table 4-7 security states sec01:sec00 description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure bit 7 6 54321 bit 0 read: 0 0 keyacc 00000 write: reset: 0 0 000000 = unimplemented or reserved figure 4-6 flash configuration register (fcnfg)
memory mc9s08gb/gt 60 motorola figure 4-7 flash protection register (fprot) fpopen open unprotected flash for program/erase 1 = any flash location, not otherwise block protected or secured, may be erased or programmed. 0 = entire flash memory is block protected (no program or erase allowed). fpdis flash protection disable 1 = no flash block is protected. 0 = flash block specified by fps2:fps0 is block protected (program and erase not allowed). fps2:fps1:fps0 flash protect size selects when fpdis = 0, this 3-bit field determines the size of a protected block of flash locations at the high address end of the flash (see table 4-8 ). protected flash locations cannot be erased or programmed. bit 7 6 54321 bit 0 read: fpopen fpdis fps2 fps1 fps0 0 0 0 write: (1) notes : 1. background commands can be used to change the contents of these bits in fprot. (1) (1) (1) (1) reset: this register is loaded from nonvolatile location nvprot during reset. = unimplemented or reserved table 4-8 high address protected block fps2:fps1:fps0 protected address range protected block size redirected vectors (1) notes : 1. no redirection if fpopen = 0, or fnored = 1. 0:0:0 $fe00?ffff 512 bytes $fdc0?fdfd (2) 2. reset vector is not redirected. 0:0:1 $fc00?ffff 1 kbytes $fbc0?fbfd 0:1:0 $f800?ffff 2 kbytes $f7c0?f7fd 0:1:1 $f000?ffff 4 kbytes $efc0?effd 1:0:0 $e000 - $ffff 8 kbytes $dfc0?dffd 1:0:1 $c000 - $ffff 16 kbytes $bfc0?bffd 1:1:0 $8000 - $ffff 32 kbytes $7fc0?7ffd 1:1:1 $8000 - $ffff 32 kbytes $7fc0?7ffd
data sheet ?mc9s08gb60/d v1.5 motorola 61 mc9s08gb/gt 4.6.5 flash status register (fstat) bits 3, 1, and 0 always read 0 and writes have no meaning or effect. the remaining five bits are status bits that can be read at any time. writes to these bits have special meanings that are discussed in the bit descriptions. figure 4-8 flash status register (fstat) fcbef flash command buffer empty flag the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a one to it or when a burst program command is transferred to the array for programming. only burst program commands can be buffered. 1 = a new burst program command may be written to the command buffer. 0 = command buffer is full (not ready for additional commands). fccf flash command complete flag fccf is set automatically when the command buffer is empty and no command is being processed. fccf is cleared automatically when a new command is started (by writing 1 to fcbef to register a command). writing to fccf has no meaning or effect. 1 = all commands complete 0 = command in progress fpviol protection violation flag fpviol is set automatically when fcbef is cleared to register a command that attempts to erase or program a location in a protected block (the erroneous command is ignored). fpviol is cleared by writing a 1 to fpviol. 1 = an attempt was made to erase or program a protected location. 0 = no protection violation. faccerr access error flag faccerr is set automatically when the proper command sequence is not followed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the fcdiv register has been initialized, or if the mcu enters stop while a command was in progress. for a more detailed discussion of the exact actions that are considered access errors, see 4.4.5 access errors . faccerr is cleared by writing a 1 to faccerr. writing a 0 to faccerr has no meaning or effect. 1 = an access error has occurred. 0 = no access error. bit 7 6 54321 bit 0 read: fcbef fccf fpviol faccerr 0 fblank 0 0 write: reset: 1 1 000000 = unimplemented or reserved
memory mc9s08gb/gt 62 motorola fblank flash verified as all blank (erased) flag fblank is set automatically at the conclusion of a blank check command if the entire flash array was verified to be erased. fblank is cleared by clearing fcbef to write a new valid command. writing to fblank has no meaning or effect. 1 = after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash array is completely erased (all $ff). 0 = after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash array is not completely erased. 4.6.6 flash command register (fcmd) only five command codes are recognized in normal user modes as shown in table 4-9 . refer to 4.4.3 program and erase command execution for a detailed discussion of flash programming and erase operations. all other command codes are illegal and generate an access error. it is not necessary to perform a blank check command after a mass erase operation. only blank check is required as part of the security unlocking mechanism. bit 7 6 54321 bit 0 read: 0 0 000000 write: fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 reset: 0 0 000000 = unimplemented or reserved figure 4-9 flash command register (fcmd) table 4-9 flash commands command fcmd equate file label blank check $05 mblank byte program $20 mbyteprog byte program ?burst mode $25 mburstprog page erase (512 bytes/page) $40 mpageerase mass erase (all flash) $41 mmasserase
data sheet ?mc9s08gb60/d v1.5 motorola 63 mc9s08gb/gt section 5 resets, interrupts, and system configuration 5.1 introduction this section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the mc9s08gb/gt. some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data manual. this section gathers basic information about all reset and interrupt sources in one place for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog and real-time interrupt (rti), are not part of on-chip peripheral systems with their own sections but are part of the system control logic. 5.2 features reset and interrupt features include: multiple sources of reset for flexible system configuration and reliable operation: power-on detection (por) low voltage detection (lvd) with enable external reset pin with enable cop watchdog with enable and two timeout choices illegal opcode serial command from a background debug host reset status register (srs) to indicate source of most recent reset separate interrupt vectors for each module (reduces polling overhead) (see table 5-1 )
resets, interrupts, and system configuration mc9s08gb/gt 64 motorola 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector ($fffe:$ffff). on-chip peripheral modules are disabled and i/o pins are initially configured as general-purpose high-impedance inputs with pullup devices disabled. the i bit in the condition code register (ccr) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (sp) and system control settings. sp is forced to $00ff at reset. the mc9s08gb/gt has seven sources for reset: power-on reset (por) low-voltage detect (lvd) computer operating properly (cop) timer illegal opcode detect background debug forced reset the reset pin ( reset) clock generator loss of lock and loss of clock reset each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. whenever the mcu enters reset, the internal clock generator (icg) module switches to self-clocked mode with the frequency of f self_reset selected. the reset pin is driven low for 34 internal bus cycles where the internal bus frequency is half the icg frequency. after the 34 cycles are completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low externally. after the pin is released, it is sampled after another 38 cycles to determine whether the reset pin is the cause of the mcu reset. 5.4 computer operating properly (cop) watchdog the cop watchdog is intended to force a system reset when the application software fails to execute as expected. to prevent a system reset from the cop timer (when it is enabled), application software must reset the cop timer periodically. if the application program gets lost and fails to reset the cop before it times out, a system reset is generated to force the system back to a known starting point. the cop watchdog is enabled by the cope bit in sopt (see 5.8.4 system options register (sopt) for additional information). the cop timer is reset by writing any value to the address of srs. this write does not affect the data in the read-only srs. instead, the act of writing to this address is decoded and sends a reset signal to the cop timer. after any reset, the cop timer is enabled. this provides a reliable way to detect code that is not executing as intended. if the cop watchdog is not used in an application, it can be disabled by clearing the cope bit in the write-once sopt register. also, the copt bit can be used to choose one of two timeout periods (2 18 or 2 13 cycles of the bus rate clock). even if the application will use the reset default settings in cope and copt, the user should still write to write-once sopt during reset initialization to lock in the settings. that way, they cannot be changed accidentally if the application program gets lost.
data sheet ?mc9s08gb60/d v1.5 motorola 65 mc9s08gb/gt the write to srs that services (clears) the cop timer should not be placed in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. when the mcu is in active background mode, the cop timer is temporarily disabled. 5.5 interrupts interrupts provide a way to save the current cpu status and registers, execute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it left off before the interrupt. other than the software interrupt (swi), which is a program instruction, interrupts are caused by hardware events such as an edge on the irq pin or a timer-overflow event. the debug module can also generate an swi under certain circumstances. if an event occurs in an enabled interrupt source, an associated read-only status flag will become set. the cpu will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. the i bit in the ccr is logic 0 to allow interrupts. the global interrupt mask (i bit) in the ccr is initially set after reset which masks (prevents) all maskable interrupt sources. the user program initializes the stack pointer and performs other system setup before clearing the i bit to allow the cpu to respond to interrupts. when the cpu receives a qualified interrupt request, it completes the current instruction before responding to the interrupt. the interrupt sequence follows the same cycle-by-cycle sequence as the swi instruction and consists of: saving the cpu registers on the stack setting the i bit in the ccr to mask further interrupts fetching the interrupt vector for the highest-priority interrupt that is currently pending filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restored from the value stacked on entry to the isr. in rare cases, the i bit may be cleared inside an isr (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. this practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. the interrupt service routine ends with a return-from-interrupt (rti) instruction which restores the ccr, a, x, and pc registers to their pre-interrupt values by reading the previously saved information off the stack. note: for compatibility with the m68hc08, the h register is not automatically saved and restored. it is good programming practice to push h onto the stack at the start of the interrupt service routine (isr) and restore it just before the rti that is used to return from the isr.
resets, interrupts, and system configuration mc9s08gb/gt 66 motorola when two or more interrupts are pending when the i bit is cleared, the highest priority source is serviced first (see table 5-1 vector summary ). 5.5.1 interrupt stack frame figure 5-1 shows the contents and organization of a stack frame. before the interrupt, the stack pointer (sp) points at the next available byte location on the stack. the current values of cpu registers are stored on the stack starting with the low-order byte of the program counter (pcl) and ending with the ccr. after stacking, the sp points at the next available location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. figure 5-1 interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu fills the instruction pipeline by reading three bytes of program information, starting from the pc address just recovered from the stack. the status flag causing the interrupt must be acknowledged (cleared) before returning from the isr. typically, the flag should be cleared at the beginning of the isr so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current isr. 5.5.2 external interrupt request (irq) pin external interrupts are managed by the irqsc status and control register. when the irq function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. when the mcu is in stop mode and system clocks are shut down, a separate asynchronous path is used so the irq (if enabled) can wake the mcu. condition code register accumulator index register (low byte x) program counter high * high byte (h) of index register is not automatically stacked. * program counter low 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt
data sheet ?mc9s08gb60/d v1.5 motorola 67 mc9s08gb/gt 5.5.2.1 pin configuration options the irq pin enable (irqpe) control bit in the irqsc register must be 1 in order for the irq pin to act as the interrupt request (irq) input. as an irq input, the user can choose the polarity of edges or levels detected (irqedg), whether the pin detects edges-only or edges and levels (irqmod), and whether an event causes an interrupt or just sets the irqf flag which can be polled by software. when the irq pin is configured to detect rising edges, an optional pulldown resistor is available rather than a pullup resistor. bih and bil instructions may be used to detect the level on the irq pin when the pin is configured to act as the irq input. note: the voltage measured on the pulled up irq pin may be as low as v dd 0.7 v. the internal gates connected to this pin are pulled all the way to v dd . all other pins with enabled pullup resistors will have an unloaded measurement of v dd . 5.5.2.2 edge and level sensitivity the irqmod control bit reconfigures the detection logic so it detects edge events and pin levels. in this edge detection mode, the irqf status flag becomes set when an edge is detected (when the irq pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the irq pin remains at the asserted level. 5.5.3 interrupt vectors, sources, and local masks table 5-1 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. when an interrupt condition occurs, an associated flag bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will finish the current instruction, stack the pcl, pch, x, a, and ccr cpu registers, set the i bit, and then fetch the interrupt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine.
resets, interrupts, and system configuration mc9s08gb/gt 68 motorola table 5-1 vector summary vector priority address (high/low) vector name module source enable description lower higher $ffc0/ffc1 through $ffca/ffcb unused vector space (available for user program) $ffcc/ffcd vrti system control rtif rtie real-time interrupt $ffce/ffcf viic iic iicis iicie iic control $ffd0/ffd1 vatd atd coco aien ad conversion complete $ffd2/ffd3 vkeyboard kbi kbf kbie keyboard pins $ffd4/ffd5 vsci2tx sci2 tdre tc tie tcie sci2 transmit $ffd6/ffd7 vsci2rx sci2 idle rdrf ilie rie sci2 receive $ffd8/ffd9 vsci2err sci2 or nf fe pf orie nfie feie pfie sci2 error $ffda/ffdb vsci1tx sci1 tdre tc tie tcie sci1 transmit $ffdc/ffdd vsci1rx sci1 idle rdrf ilie rie sci1 receive $ffde/ffdf vsci1err sci1 or nf fe pf orie nfie feie pfie sci1 error $ffe0/ffe1 vspi spi spif modf sptef spie spie sptie spi $ffe2/ffe3 vtpm2ovf tpm2 tof toie tpm2 over?w $ffe4/ffe5 vtpm2ch4 tpm2 ch4f ch4ie tpm2 channel 4 $ffe6/ffe7 vtpm2ch3 tpm2 ch3f ch3ie tpm2 channel 3 $ffe8/ffe9 vtpm2ch2 tpm2 ch2f ch2ie tpm2 channel 2 $ffea/ffeb vtpm2ch1 tpm2 ch1f ch1ie tpm2 channel 1 $ffec/ffed vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 $ffee/ffef vtpm1ovf tpm1 tof toie tpm1 over?w $fff0/fff1 vtpm1ch2 tpm1 ch2f ch2ie tpm1 channel 2 $fff2/fff3 vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 $fff4/fff5 vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 $fff6/fff7 vicg icg icgif (lols/locs) lolre/locre icg $fff8/fff9 vlvd system control lvdf lvdie low-voltage detect $fffa/fffb virq irq irqf irqie irq pin $fffc/fffd vswi core swi instruction software interrupt $fffe/ffff vreset system control cop lv d reset pin illegal opcode cope lvdre watchdog timer low-voltage detect external pin illegal opcode
data sheet ?mc9s08gb60/d v1.5 motorola 69 mc9s08gb/gt 5.6 low-voltage detect (lvd) system the mc9s08gb/gt includes a system to protect against low voltage conditions in order to protect memory contents and control mcu system states during supply voltage variations. the system is comprised of a power-on reset (por) circuit and an lvd circuit with a user selectable trip voltage, either high (v lvdh ) or low (v lvdl ). the lvd circuit is enabled when lvde in spmsc1 is high and the trip voltage is selected by lvdv in spmsc2. the lvd is disabled upon entering any of the stop modes unless the lvdse bit is set. if lvdse and lvde are both set, then the mcu cannot enter stop1 or stop2, and the current consumption in stop3 with the lvd enabled will be greater. 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply voltage drops below the v por level, the por circuit will cause a reset condition. as the supply voltage rises, the lvd circuit will hold the chip in reset until the supply has risen above the v lvdh level. both the por bit and the lvd bit in srs are set following a por. 5.6.2 lvd reset operation the lvd can be configured to generate a reset upon detection of a low voltage condition by setting lvdre to 1. once an lvd reset has occurred, the lvd system will hold the mcu in reset until the supply voltage has risen above the level determined by lvdv. the lvd bit in the srs register is set following either an lvd reset or por. 5.6.3 lvd interrupt operation when a low voltage condition is detected and the lvd circuit is configured for interrupt operation (lvde set, lvdie set, and lvdre clear), then lvdf will be set and an lvd interrupt will occur. 5.6.4 low-voltage warning (lvw) the lvd system has a low voltage warning flag to indicate to the user that the supply voltage is approaching, but is still above, the lvd voltage. the lvw does not have an interrupt associated with it. there are two user selectable trip voltages for the lvw, one high (v lvwh ) and one low (v lvwl ). the trip voltage is selected by lvwv in spmsc2. 5.7 real-time interrupt (rti) the real-time interrupt function can be used to generate periodic interrupts based on a divide of the external oscillator during run mode. it can also be used to wake the mcu from stop2 mode or stop3 mode. the rti control includes an internal 1-khz clock source. wakeup from stop2 can only be done using this internal clock. wakeup from stop3 can be done using either the 1-khz clock or the external oscillator. when using the external oscillator, it must be enabled in stop (oscsten = 1) and configured for low bandwidth operation (range = 0).
resets, interrupts, and system configuration mc9s08gb/gt 70 motorola the srtisc register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value (rtis2:rtis1:rtis0) used to disable the clock source to the real-time interrupt or select one of seven wakeup delays between 8 ms and 1.024 seconds. the 1-khz clock source and therefore the periodic rates have a tolerance of about 30 percent. the rti has a local interrupt enable, rtie, to allow masking of the real-time interrupt. it can be disabled by writing 0:0:0 to rtis2:rtis1:rtis0 so the clock source is disabled and no interrupts will be generated. see 5.8.6 system real-time interrupt status and control register (srtisc) for detailed information about this register. 5.8 reset, interrupt, and system control registers and control bits one 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. some control bits in the sopt and spmsc2 registers are related to modes of operation. although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in section 3 modes of operation . 5.8.1 interrupt pin request status and control register (irqsc) this direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and one write-only bit. these bits are used to configure the irq function, report status, and acknowledge irq events. figure 5-2 interrupt request status and control register (irqsc) irqedg interrupt request (irq) edge select this read/write control bit is used to select the polarity of edges or levels on the irq pin that cause irqf to be set. the irqmod control bit determines whether the irq pin is sensitive to both edges and levels or just edges. when the irq pin is enabled as the irq input and is configured to detect rising edges, the optional pullup resistor is reconfigured as an optional pulldown resistor. 1 = irq is rising edge or rising edge/high-level sensitive. 0 = irq is falling edge or falling edge/low-level sensitive. bit 7 654321 bit 0 read: 0 0 irqedg irqpe irqf 0 irqie irqmod write: irqack reset: 00000000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 71 mc9s08gb/gt irqpe irq pin enable this read/write control bit enables the irq pin function. when this bit is set the irq pin can be used as an interrupt request. also, when this bit is set, either an internal pull-up or an internal pull-down resistor is enabled depending on the state of the irqmod bit. 1 = irq pin function is enabled. 0 = irq pin function is disabled. irqf irq flag this read-only status bit indicates when an interrupt request event has occurred. 1 = irq event detected. 0 = no irq request. irqack irq acknowledge this write-only bit is used to acknowledge interrupt request events (write 1 to clear irqf). writing 0 has no meaning or effect. reads always return logic 0. if edge-and-level detection is selected (irqmod = 1), irqf cannot be cleared while the irq pin remains at its asserted level. irqie irq interrupt enable this read/write control bit determines whether irq events generate a hardware interrupt request. 1 = hardware interrupt requested whenever irqf = 1. 0 = hardware interrupt requests from irqf disabled (use polling). irqmod irq detection mode this read/write control bit selects either edge-only detection or edge-and-level detection. the irqedg control bit determines the polarity of edges and levels that are detected as interrupt request events. see 5.5.2.2 edge and level sensitivity for more details. 1 = irq event on falling edges and low levels or on rising edges and high levels. 0 = irq event on falling edges or rising edges only. 5.8.2 system reset status register (srs) this register includes seven read-only status flags to indicate the source of the most recent reset. when a debug host forces reset by writing 1 to bdfr in the sbdfr register, none of the status bits in srs will be set. writing any value to this register address clears the cop watchdog timer without affecting the contents of this register. the reset state of these bits depends on what caused the mcu to reset.
resets, interrupts, and system configuration mc9s08gb/gt 72 motorola figure 5-3 system reset status (srs) por power-on reset reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvd) status bit is also set to indicate that the reset occurred while the internal supply was below the lvd threshold. 1 = por caused reset. 0 = reset not caused by por. pin external reset pin reset was caused by an active-low level on the external reset pin. 1 = reset came from external reset pin. 0 = reset not caused by external reset pin. cop computer operating properly (cop) watchdog reset was caused by the cop watchdog timer timing out. this reset source may be blocked by cope = 0. 1 = reset caused by cop timeout. 0 = reset not caused by cop timeout. ilop illegal opcode reset was caused by an attempt to execute an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt register. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 1 = reset caused by an illegal opcode. 0 = reset not caused by an illegal opcode. icg internal clock generation module reset reset was caused by an icg module reset. 1 = reset caused by icg module. 0 = reset not caused by icg module. bit 7 6 54321 bit 0 read: por pin cop ilop 0 icg lvd 0 write: writing any value to simrs address clears cop watchdog timer. power-on reset: 1 0 000010 low-voltage reset: u 0 000010 any other reset: 0 (1) notes : 1. any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset will be cleared. (1) (1) 0 (1) 00 u = unaffected by reset
data sheet ?mc9s08gb60/d v1.5 motorola 73 mc9s08gb/gt lvd low voltage detect if the lvd reset is enabled (lvde = lvdre = 1) and the supply drops below the lvd trip voltage, an lvd reset occurs. the lvd function is disabled when the mcu enters stop. to maintain lvd operation in stop, the lvdse bit must be set. 1 = reset caused by lvd trip or por. 0 = reset not caused by lvd trip or por. 5.8.3 system background debug force reset register (sbdfr) this register contains a single write-only control bit. a serial background command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return $00. figure 5-4 system background debug force reset register (sbdfr) bdfr background debug force reset a serial background command such as write_byte may be used to allow an external debug host to force a target system reset. writing logic 1 to this bit forces an mcu reset. this bit cannot be written from a user program. 5.8.4 system options register (sopt) this register may be read at any time. bits 3 and 2 are unimplemented and always read 0. this is a write-once register so only the first write after reset is honored. any subsequent attempt to write to sopt (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. sopt should be written during the user? reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. bit 7 654321 bit 0 read: 00000000 write: bdfr (1) notes : 1. bdfr is writable only through serial background debug commands, not from user programs. reset: 00000000 = unimplemented or reserved bit 7 654321 bit 0 read: cope copt stope 00 bkgdpe write: reset: 11010011 = unimplemented or reserved figure 5-5 system options register (sopt)
resets, interrupts, and system configuration mc9s08gb/gt 74 motorola cope cop watchdog enable this write-once bit defaults to 1 after reset. 1 = cop watchdog timer enabled (force reset on timeout). 0 = cop watchdog timer disabled. copt cop watchdog timeout this write-once bit defaults to 1 after reset. 1 = long timeout period selected (2 18 cycles of busclk). 0 = short timeout period selected (2 13 cycles of busclk). stope stop mode enable this write-once bit defaults to 0 after reset, which disables stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 1 = stop mode enabled. 0 = stop mode disabled. bkgdpe background debug mode pin enable the bkgdpe bit enables the ptd0/bkgd/ms pin to function as bkgd/ms. when the bit is clear, the pin will function as ptd0, which is an output only general purpose i/o. this pin always defaults to bkgd/ms function after any reset. 1 = bkgd pin enabled. 0 = bkgd pin disabled.
data sheet ?mc9s08gb60/d v1.5 motorola 75 mc9s08gb/gt 5.8.5 system device identification register (sdidh, sdidl) this read-only register is included so host development systems can identify the hcs08 derivative and revision number. this allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target mcu. figure 5-6 system device identification register (sdidh, sdidl) rev[3:0] revision number the high-order 4 bits of address $1806 are hard coded to reflect the current mask set revision number (0?). id[11:0] part identification number each derivative in the hcs08 family has a unique identification number. the mc9s08gb/gt is hard coded to the value $002. 5.8.6 system real-time interrupt status and control register (srtisc) this register contains one read-only status flag, one write-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. figure 5-7 system rti status and control register (srtisc) bit 7 6 5 4321 bit 0 read: rev3 rev2 rev1 rev0 id11 id10 id9 id8 reset: 0 (1) notes : 1. the revision number that is hard coded into these bits reflects the current silicon revision level. 0 (1) 0 (1) 0 (1) 0000 read: id7 id6 id5 id4 id3 id2 id1 id0 reset: 0 0 0 00010 = unimplemented or reserved bit 7 6 5 4321 bit 0 read: rtif 0 rticlks rtie 0 rtis2 rtis1 rtis0 write: rtiack reset: 0 0 0 00000 = unimplemented or reserved
resets, interrupts, and system configuration mc9s08gb/gt 76 motorola rtif real-time interrupt flag this read-only status bit indicates the periodic wakeup timer has timed out. 1 = periodic wakeup timer timed out. 0 = periodic wakeup timer not timed out. rtiack real-time interrupt acknowledge this write-only bit is used to acknowledge real-time interrupt request (write 1 to clear rtif). writing 0 has no meaning or effect. reads always return logic 0. rticlks real-time interrupt clock select this read/write bit selects the clock source for the real-time interrupt. 1 = real-time interrupt request clock source is external clock. 0 = real-time interrupt request clock source is internal 1-khz oscillator. rtie real-time interrupt enable this read-write bit enables real-time interrupts. 1 = real-time interrupts enabled. 0 = real-time interrupts disabled. rtis2:rtis1:rtis0 real-time interrupt delay selects these read/write bits select the wakeup delay for the rti. the clock source for the real-time interrupt is a self-clocked source which oscillates at about 1 khz, is independent of other mcu clock sources. using external clock source the delays will be crystal frequency divided by value in rtis2:rtis1:rtis0. table 5-2 real-time interrupt frequency rtis2:rtis1:rtis0 1-khz clock source delay (1) notes : 1. normal values are shown in this column based on f rti = 1 khz. see table a-10 control timing f rti for the tolerance on these values. using external clock source delay (crystal frequency) 0:0:0 disable periodic wakeup timer disable periodic wakeup timer 0:0:1 8 ms divide by 256 0:1:0 32 ms divide by 1024 0:1:1 64 ms divide by 2048 1:0:0 128 ms divide by 4096 1:0:1 256 ms divide by 8192 1:1:0 512 ms divide by 16384 1:1:1 1.024 s divide by 32768
data sheet ?mc9s08gb60/d v1.5 motorola 77 mc9s08gb/gt 5.8.7 system power management status and control 1 register (spmsc1) figure 5-8 system power management status and control 1 register (spmsc1) lvdf low-voltage detect flag provided lvde = 1, this read-only status bit indicates a low-voltage detect event. lvdack low-voltage detect acknowledge this write-only bit is used to acknowledge low voltage detection errors (write 1 to clear lvdf). reads always return logic 0. lvdie low-voltage detect interrupt enable this read/write bit enables hardware interrupt requests for lvdf. 1 = request a hardware interrupt when lvdf = 1. 0 = hardware interrupt disabled (use polling). lvdre low-voltage detect reset enable this read/write bit enables lvdf events to generate a hardware reset (provided lvde = 1). 1 = force an mcu reset when lvdf = 1. 0 = lvdf does not generate hardware resets. lvdse low-voltage detect stop enable provided lvde = 1, this read/write bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 1 = low-voltage detect enabled during stop mode. 0 = low-voltage detect disabled during stop mode. lvde low-voltage detect enable this read/write bit enables low-voltage detect logic and qualifies the operation of other bits in this register. 1 = lvd logic enabled. 0 = lvd logic disabled. bit 7 6 54321 bit 0 read: lvdf 0 lvdie lvdre (1) notes : 1. this bit can be written only one time after reset. additional writes are ignored. lvdse (1) lvde (1) 00 write: lvdack reset: 0 0 011100 = unimplemented or reserved
resets, interrupts, and system configuration mc9s08gb/gt 78 motorola 5.8.8 system power management status and control 2 register (spmsc2) this register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the mcu. figure 5-9 system power management status and control 2 register (spmsc2) lvwf low-voltage warning flag the lvwf bit indicates the low voltage warning status. 1 = low voltage warning is present or was present. 0 = low voltage warning not present. lvwack low-voltage warning acknowledge the lvwf bit indicates the low voltage warning status. writing a logic 1 to lvwack clears lvwf to a logic 0 if a low voltage warning is not present. lvdv low-voltage detect voltage select the lvdv bit selects the lvd trip point voltage (v lvd ). 1 = high trip point selected (v lvd = v lvdh ). 0 = low trip point selected (v lvd = v lvdl ). lvwv low-voltage warning voltage select the lvwv bit selects the lvw trip point voltage (v lvw ). 1 = high trip point selected (v lvw = v lvwh ). 0 = low trip point selected (v lvw = v lvwl ). ppdf partial power down flag the ppdf bit indicates that the mcu has exited the stop2 mode. 1 = stop2 mode recovery. 0 = not stop2 mode recovery. bit 7 6 54321 bit 0 read: lvwf 0 lvdv lvwv ppdf 0 pdc ppdc write: lvwack ppdack power-on reset: 0 (1) notes : 1. lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lvw . 0 00 0000 lvd reset: 0 (1) 0 uu0000 any other reset: 0 (1) 0 uu0000 = unimplemented or reserved u = unaffected by reset
data sheet ?mc9s08gb60/d v1.5 motorola 79 mc9s08gb/gt ppdack partial power down acknowledge writing a logic 1 to ppdack clears the ppdf bit. pdc ?power down control the write-once pdc bit controls entry into the power down (stop2 and stop1) modes. 1 = power down modes are enabled. 0 = power down modes are disabled. ppdc ?partial power down control the write-once ppdc bit controls which power down mode, stop1 or stop2, is selected. 1 = stop2, partial power down, mode enabled if pdc set. 0 = stop1, full power down, mode enabled if pdc set.
resets, interrupts, and system configuration mc9s08gb/gt 80 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 81 mc9s08gb/gt section 6 internal clock generator (icg) module the mc9s08gb/gt microcontroller provides one internal clock generation (icg) module to create the system bus frequency. all functions described in this section are available on the mc9s08gb/gt microcontroller. the extal and xtal pins share port g bits 2 and 1, respectively. analog supply lines v dda and v ssa are internally derived from the mcu? v dd and v ss pins. electrical parametric data for the icg may be found in the electrical characteristics appendix. figure 6-1 system clock distribution diagram note: motorola recommends that flash location $ffbe be reserved to store a nonvolatile version of icgtrm. this will allow debugger and programmer vendors to perform a manual trim operation and store the resultant icgtrm value for users to access at a later time. tpm1 tpm2 iic sci1 sci2 spi bdc cpu atd ram flash icg icgout 2 ffe system logic busclk icglclk* atd has min and max frequency requirements. see atd section and flash has frequency requirements for program and erase operation. see appendix a. appendix a. control fixed freq clock (xclk) icgerclk rti * icglclk is the alternate bdc clock source for the mc9s08gb/gt.
internal clock generator (icg) moduleinternal clock generator (icg) module mc9s08gb/gt 82 motorola figure 6-2 block diagram highlighting icg module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core cpu notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5 bdc
data sheet ?mc9s08gb60/d v1.5 motorola 83 mc9s08gb/gt 6.1 introduction figure 6-3 is a top-level diagram that shows the functional organization of the internal clock generation (icg) module. this section includes a general description and a feature list. figure 6-3 icg block diagram the icg provides multiple options for clock sources. this offers a user great flexibility when making choices between cost, precision, current draw, and performance. as seen in figure 6-3 , the icg consists of four functional blocks. each of these is briefly described here and then in more detail in a later section. oscillator block ?the oscillator block provides means for connecting an external crystal or resonator. two frequency ranges are software selectable to allow optimal startup and stability. alternatively, the oscillator block can be used to route an external square wave to the system clock. external sources can provide a very precise clock source. internal reference generator the internal reference generator consists of two controlled clock sources. one is designed to be approximately 8 mhz and can be selected as a local clock for the background debug controller. the other internal reference clock source is typically 243 khz and can be trimmed for finer accuracy via software when a precise timed event is input to the mcu. this provides a highly reliable, low-cost clock source. oscillator (osc) frequency internal extal xtal reference generators clock select 8 mhz irg loss of lock and clock detector locked loop (fll) fixed clock select icgout typ 243 khz rg icglclk icg ffe v dda v ssa (see note 2) (see note 2) dco with external ref select ref select local clock for optional use with bdc output clock select icgdclk /r icgerclk icgirclk notes: 1. see chip level clock routing diagram for specific use of icgout, ffe, icglclk, icgerclk 2. not all hcs08 microcontrollers have unique supply pins for the icg. see the device pin assignments in the pins and connections section for specifics.
internal clock generator (icg) module mc9s08gb/gt 84 motorola frequency-locked loop ?a frequency-locked loop (fll) stage takes either the internal or external clock source and multiplies it to a higher frequency. status bits provide information when the circuit has achieved lock and when it falls out of lock. additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. clock select block ?the clock select block provides several switch options for connecting different clock sources to the system clock tree. icgdclk is the multiplied clock frequency out of the fll, icgerclk is the reference clock frequency from the crystal or external clock source, and ffe (fixed frequency enable) is a control signal used to control the system fixed frequency clock (xclk). icglclk is the clock source for the background debug controller (bdc). the module is intended to be very user friendly with many of the features occurring automatically without user intervention. to quickly configure the module, go to initialization/application information and pick an example that best suits the application needs. 6.1.1 features features of the icg and clock distribution system: several options for the primary clock source allow a wide range of cost, frequency, and precision choices: 32 khz?00 khz crystal or resonator 1 mhz?6 mhz crystal or resonator external clock internal reference generator defaults to self-clocked mode to minimize startup delays frequency-locked loop (fll) generates 8 mhz to 40 mhz (for bus rates up to 20 mhz) uses external or internal clock as reference frequency automatic lockout of non-running clock sources reset or interrupt on loss of clock or loss of fll lock digitally-controlled oscillator (dco) preserves previous frequency settings, allowing fast frequency lock when recovering from stop3 mode dco will maintain operating frequency during a loss or removal of reference clock post-fll divider selects 1 of 8 bus rate divisors (/1 through /128) separate self-clocked source for real-time interrupt trimmable internal clock source supports sci communications without additional external components automatic fll engagement after lock is acquired
data sheet ?mc9s08gb60/d v1.5 motorola 85 mc9s08gb/gt 6.1.2 modes of operation this is a high-level description only. detailed descriptions of operating modes are contained in 6.3 functional description mode 1 ?off the output clock, icgout, is static. this mode may be entered when the stop instruction is executed. mode 2 ?self-clocked (scm) default mode of operation that is entered out of reset. the icg? fll is open loop and the digitally controlled oscillator (dco) is free running at a frequency set by the filter bits. mode 3 ?fll engaged internal (fei) in this mode, the icg? fll is used to create frequencies that are programmable multiples of the internal reference clock. fll engaged internal unlocked is a transition state which occurs while the fll is attempting to lock. the fll dco frequency is off target and the fll is adjusting the dco to match the target frequency. fll engaged internal locked is a state which occurs when the fll detects that the dco is locked to a multiple of the internal reference. mode 4 ?fll bypassed external (fbe) in this mode, the icg is configured to bypass the fll and use an external clock as the clock source. mode 5 ?fll engaged external (fee) the icg? fll is used to generate frequencies that are programmable multiples of the external clock reference. fll engaged external unlocked is a transition state which occurs while the fll is attempting to lock. the fll dco frequency is off target and the fll is adjusting the dco to match the target frequency. fll engaged external locked is a state which occurs when the fll detects that the dco is locked to a multiple of the internal reference. 6.2 external signal description 6.2.1 overview table 6-1 shows the user-accessible signals available for the icg.
internal clock generator (icg) module mc9s08gb/gt 86 motorola 6.2.2 detailed signal descriptions this section describes each pin signal in detail. 6.2.2.1 extal?external reference clock / oscillator input if the first write to the icg control register 1 selected fll engaged external or fll bypassed modes, this signal is the analog external/reference clock or the input of the oscillator circuit. if the first write to the icg control register 1 selected fll engaged internal or self-clocked modes, this signal has no effect on the icg. 6.2.2.2 xtal?oscillator output if the first write to the icg control register 1 selected fll engaged external or fll bypassed modes using a crystal/resonator reference, this signal is the analog output of the oscillator amplifier circuit. in all other cases, this signal has no effect on the icg. 6.2.3 external clock connections if an external clock is used, then the pins are connected as shown below. figure 6-4 external clock connections table 6-1 signal properties name function reset state extal external clock/oscillator input analog input xtal oscillator output analog output icg xtal extal v ss clock input not connected
data sheet ?mc9s08gb60/d v1.5 motorola 87 mc9s08gb/gt 6.2.4 external crystal/resonator connections if an external crystal/resonator frequency reference is used, then the pins are connected as shown below. recommended component values are listed in the electrical characteristics section. figure 6-5 external frequency reference connection 6.3 functional description this section provides a functional description of each of the five operating modes of the icg. also covered are the loss of clock and loss of lock errors and requirements for entry into each mode. 6.3.1 off mode (off) normally when the cpu enters stop mode, the icg will cease all clock activity and is in the off state. however there are two cases to consider when clock activity continues while the cpu is in stop mode, 6.3.1.1 bdm active when the bdm is enabled (enbdm = 1), the icg continues activity as originally programmed. this allows access to memory and control registers via the bdc controller. icg extal xtal v ss c 1 c 2 crystal or resonator r f r s
internal clock generator (icg) module mc9s08gb/gt 88 motorola 6.3.1.2 oscsten bit set when the oscillator is enabled in stop mode (oscsten = 1), the individual clock generators are enabled but the clock feed to the rest of the mcu is turned off. this option is provided to avoid long oscillator startup times if necessary, or to run the rti from the oscillator during stop3. 6.3.1.3 stop/off mode recovery upon the cpu exiting stop mode due to an interrupt, the previously set control bits are valid and the system clock feed resumes. if fee is selected, the icg will source the internal reference until the external clock is stable. if fbe is selected, the icg will wait for the external clock to stabilize before enabling icgout. upon the cpu exiting stop mode due to a reset, the previously set icg control bits are ignored and the default reset values applied. therefore the icg will exit stop in scm mode configured for an approximately 8 mhz dco output (4 mhz bus clock) with trim value maintained. if using a crystal, 4096 clocks are detected prior to engaging icgerclk. this is incorporated in crystal start-up time. 6.3.2 self-clocked mode (scm) self-clocked mode (scm) is the default mode of operation and is entered when any of the following conditions occur: after any reset. exiting from off mode when clks does not equal 10. if clks = x1, the icg enters this state temporarily until the dco is stable (dcos = 1). clks bits are written from x1 to 00. clks = 1x and icgerclk is not detected (both ercs = 0 and locs = 1). in this state, the fll loop is open. the dco is on, and the output clock signal icgout frequency is given by f icgdclk / r. the icgdclk frequency can be varied from 8 mhz to 40 mhz by writing a new value into the filter registers (icgflth and icgfltl). this is the only mode in which the filter registers can be written. if this mode is entered due to a reset, f icgdclk will default to f self_reset which is nominally 8 mhz. if this mode is entered from fll engaged internal, f icgdclk will maintain the previous frequency.if this mode is entered from fll engaged external (either by programming clks or due to a loss of external reference clock), f icgdclk will maintain the previous frequency, but icgout will double if the fll was unlocked. if this mode is entered from off mode, f icgdclk will be equal to the frequency of icgdclk before entering off mode. if clks bits are set to 01 or 11 coming out of the off state, the icg enters this mode until icgdclk is stable as determined by the dcos bit. once icgdclk is considered stable, the icg automatically closes the loop by switching to fll engaged (internal or external) as selected by the clks bits.
data sheet ?mc9s08gb60/d v1.5 motorola 89 mc9s08gb/gt figure 6-6 detailed frequency-locked loop block diagram reference divider (/7) rfd clkst subtractor loop filter digitally controlled oscillator clock icgout icg2dclk reset and interrupt irq fll analog select circuit lols pulse counter mfd frequency- icgerclk locs lock and detector lock control lolre locre reset reduced frequency divider (r) loss of clock icgif ercs icgdclk loop (fll) digital flt counter enable locked overflow 1x 2x icgirclk clkst dcos range range clks
internal clock generator (icg) module mc9s08gb/gt 90 motorola 6.3.3 fll engaged, internal clock (fei) mode fll engaged internal (fei) is entered when any of the following conditions occur: clks bits are written to 01 the dco clock stabilizes (dcos = 1) while in scm upon exiting the off state with clks = 01 in fll engaged internal mode, the reference clock is derived from the internal reference clock icgirclk, and the fll loop will attempt to lock the icgdclk frequency to the desired value, as selected by the mfd bits. 6.3.3.1 fll engaged internal unlocked fei unlocked is a temporary state that is entered when fei is entered and the count error ( ? n) output from the subtractor is greater than the maximum n unlock or less than the minimum n unlock , as required by the lock detector to detect the unlock condition. the icg will remain in this state while the count error ( ? n) is greater than the maximum n lock or less than the minimum n lock , as required by the lock detector to detect the lock condition. in this state the output clock signal icgout frequency is given by f icgdclk / r. 6.3.3.2 fll engaged internal locked fll engaged internal locked is entered from fei unlocked when the count error ( ? n), which comes from the subtractor, is less than n lock (max) and greater than nlock (min) for a given number of samples, as required by the lock detector to detect the lock condition. the output clock signal icgout frequency is given by f icgdclk / r. in fei locked, the filter value is only updated once every four comparison cycles. the update made is an average of the error measurements taken in the four previous comparisons. 6.3.4 fll bypassed, external clock (fbe) mode fll bypassed external (fbe) is entered when any of the following conditions occur: from scm when clks = 10 and ercs is high when clks = 10, ercs = 1 upon entering off mode, and off is then exited from fll engaged external mode if a loss of dco clock occurs and the external reference is still valid (both locs = 1 and ercs = 1) in this state, the dco and irg are off and the reference clock is derived from the external reference clock, icgerclk. the output clock signal icgout frequency is given by f icgerclk / r. if an external clock source is used (refs = 0), then the input frequency on the extal pin can be anywhere in the range 0 mhz to 40 mhz. if a crystal or resonator is used (refs = 1), then frequency range is either low for range = 0 or high for range = 1.
data sheet ?mc9s08gb60/d v1.5 motorola 91 mc9s08gb/gt 6.3.5 fll engaged, external clock (fee) mode the fll engaged external (fee) mode is entered when any of the following conditions occur: clks = 11 and ercs and dcos are both high. the dco stabilizes (dcos = 1) while in scm upon exiting the off state with clks = 11. in fee mode, the reference clock is derived from the external reference clock icgerclk, and the fll loop will attempt to lock the icgdclk frequency to the desired value, as selected by the mfd bits. to run in fee mode, there must be a working 32 khz?00 khz or 2 mhz?0 mhz external clock source. the maximum external clock frequency is limited to 10 mhz in fee mode to prevent over-clocking the dco. the minimum multiplier for the fll, from table 6-8 is 4. since 4 x 10 mhz is 40mhz, which is the operational limit of the dco, the reference clock cannot be any faster than 10 mhz. 6.3.5.1 fll engaged external unlocked fee unlocked is entered when fee is entered and the count error ( ? n) output from the subtractor is greater than the maximum n unlock or less than the minimum n unlock , as required by the lock detector to detect the unlock condition. the icg will remain in this state while the count error ( ? n) is greater than the maximum n lock or less than the minimum n lock , as required by the lock detector to detect the lock condition. in this state, the pulse counter, subtractor, digital loop filter, and dco form a closed loop and attempt to lock it according to their operational descriptions later in this section. upon entering this state and until the fll becomes locked, the output clock signal icgout frequency is given by f icgdclk / (2 r) this extra divide by two prevents frequency overshoots during the initial locking process from exceeding chip-level maximum frequency specifications. once the fll has locked, if an unexpected loss of lock causes it to re-enter the unlocked state while the icg remains in fee mode, the output clock signal icgout frequency is given by f icgdclk / r. 6.3.5.2 fll engaged external locked fee locked is entered from fee unlocked when the count error ( ? n) is less than n lock (max) and greater than n lock (min) for a given number of samples, as required by the lock detector to detect the lock condition. the output clock signal icgout frequency is given by f icgdclk /r. in fll engaged external locked, the filter value is only updated once every four comparison cycles. the update made is an average of the error measurements taken in the four previous comparisons. 6.3.6 fll lock and loss-of-lock detection to determine the fll locked and loss-of-lock conditions, the pulse counter counts the pulses of the dco for one comparison cycle (see table 6-3 for explanation of a comparison cycle) and passes this number to the subtractor. the subtractor compares this value to the value in mfd and produces a count error, ? n. to achieve locked status, ? n must be between n lock (min) and n lock (max). once the fll has locked, ? n must stay between n unlock (min) and n unlock (max) to remain locked. if ? n goes outside this range unexpectedly, the lols status bit is set and remains set until acknowledged or until the mcu is reset.
internal clock generator (icg) module mc9s08gb/gt 92 motorola if the icg enters the off state due to stop mode when enbdm = oscsten = 0, the fll loses locked status (lock is cleared), but lols remains unchanged because this is not an unexpected loss-of-lock condition. though it would be unusual, if enbdm is cleared to 0 while the mcu is in stop, the icg enters the off state. since this is an unexpected stopping of clocks, lols will be set when the mcu wakes up from stop. expected loss of lock occurs when the mfd or clks bits are changed or in fei mode only, when the trim bits are changed. in these cases, the lock bit will be cleared until the fll regains lock, but the lols will not be set. 6.3.7 fll loss-of-clock detection the reference clock and the dco clock are monitored under different conditions (see table 6-2 ). provided the reference frequency is being monitored, ercs = 1 indicates that the reference clock meets minimum frequency requirements. when the reference and/or dco clock(s) are being monitored, if either one falls below a certain frequency, f lor and f lod , respectively, the locs status bit will be set to indicate the error. locs will remain set until it is acknowledged or until the mcu is reset. if the icg is in fee mode when a loss of clock occurs and the ercs is still set to 1, then the clkst bits are set to 10 and the icg reverts to fbe mode. a loss of clock will also cause a loss of lock when in fee or fei modes. since the method of clearing the locs and lols bits is the same, this would only be an issue in the unlikely case that lolre = 1 and locre = 0. in this case, the interrupt would be overridden by the reset for the loss of lock. table 6-2 clock monitoring mode clks refst ercs external reference clock monitored? dco clock monitored? off 0x or 11 x forced low no no 10 0 forced low no no 10 1 real-time (1) notes : 1. if enable is high (waiting for external crystal start-up after exiting stop). ye s (1) no scm (clkst = 00) 0x x forced low no ye s (2) 2. dco clock will not be monitored until dcos = 1 upon entering scm from off or fll bypassed external mode. 10 0 forced high no ye s (2) 10 1 real-time yes ye s (2) 11 x real-time yes ye s (2) fei (clkst = 01) 0x x forced low no yes 11 x real-time yes yes fbe (clkst = 10) 10 0 forced high no no 10 1 real-time yes no fee (clkst = 11) 11 x real-time yes yes
data sheet ?mc9s08gb60/d v1.5 motorola 93 mc9s08gb/gt 6.3.8 clock mode requirements a clock mode is requested by writing to clks1:clks0 and the actual clock mode is indicated by clkst1:clkst0. provided minimum conditions are met, the status shown in clkst1:clkst0 should be the same as the requested mode in clks1:clks0. table 6-3 shows the relationship between clks, clkst, and icgout. it also shows the conditions for clks = clkst or the reason clks clkst. note: if a crystal will be used before the next reset, then be sure to set refs = 1 and clks = 1x on the first write to the icgc1 register. failure to do so will result in ?ocking refs = 0 which will prevent the oscillator amplifier from being enabled until the next reset occurs. table 6-3 icg state table actual mode (clkst) desired mode (clks) range reference frequency (f reference ) comparison cycle time icgout conditions (1) for clks = clkst notes : 1. clkst will not update immediately after a write to clks. several bus cycles are required before clkst updates to the new value. reason clks1 = clkst off (xx) off (xx) x0 0 fbe (10) x 0 0 ercs = 0 scm (00) scm (00) x f icgirclk /7 (2) 2. the reference frequency has no effect on icgout in scm, but the reference frequency is still used in making the comparisons that determine the dcos bit 8/f icgirclk icgdclk/r not switching from fbe to scm fei (01) 0 f icgirclk /7 (1) 8/f icgirclk icgdclk/r dcos = 0 fbe (10) x f icgirclk /7 (1) 8/f icgirclk icgdclk/r ercs = 0 fee (11) x f icgirclk /7 (1) 8/f icgirclk icgdclk/r dcos = 0 or ercs = 0 fei (01) fei (01) 0 f icgirclk /7 8/f icgirclk icgdclk/r dcos = 1 fee (11) x f icgirclk /7 8/f icgirclk icgdclk/r ercs = 0 fbe (10) fbe (10) x 0 icgerclk/r ercs = 1 fee (11) x 0 icgerclk/r locs = 1 & ercs = 1 fee (11) fee (11) 0 f icgerclk 2/f icgerclk icgdclk/r (3) 3. after initial lock; will be icgdclk/2r during initial locking process and while fll is re-locking after the mfd bits are changed. ercs = 1 and dcos = 1 1 f icgerclk 128/f icgerclk icgdclk/r (2) ercs = 1 and dcos = 1
internal clock generator (icg) module mc9s08gb/gt 94 motorola 6.4 initialization/application information 6.4.1 introduction the section is intended to give some basic direction on which configuration a user would want to select when initializing the icg. for some applications, the serial communication link may dictate the accuracy of the clock reference. for other applications, lowest power consumption may be the chief clock consideration. still others may have lowest cost as the primary goal. the icg allows great flexibility in choosing which is best for any application. the following sections contain initialization examples for various configurations. note: hexadecimal values designated by a preceding $, binary values designated by a preceding %, and decimal values have no preceding character. important configuration information is repeated here for reference sake. table 6-4 icg configuration consideration clock reference source = internal clock reference source = external fll engaged fei 4 mhz < f bus < 20 mhz. medium power (will be less than fee if oscillator range = high) medium clock accuracy (after irg is trimmed) lo west system cost (no external components required) irg is on. dco is on. (1) notes : 1. the irg typically consumes 100 a. the fll and dco typically consumes 0.5 to 2.5 ma, depending upon output frequency. for minimum power consumption and minimum jitter, choose n and r to be as small as possible. fee 4 mhz < f bus < 20 mhz medium power (will be less than fei if oscillator range = low) good clock accuracy medium/high system cost (crystal, resonator or external clock source required) irg is off. dco is on. fll bypassed scm this mode is mainly provided for quick and reliable system startup. 3 mhz < f bus < 5 mhz (default). 3 mhz < f bus < 20 mhz (via ?ter bits). medium power poor accuracy. irg is off. dco is on and open loop. fbe f bus range <= 8 mhz when crystal or resonator is used. lo west po wer highest clock accuracy medium/high system cost (crystal, resonator or external clock source required) irg is off. dco is off.
data sheet ?mc9s08gb60/d v1.5 motorola 95 mc9s08gb/gt figure 6-7 icg register set table 6-5 icgout frequency calculation options clock scheme f icgout p note scm ?self-clocked mode (fll bypassed internal) f icgdclk / r na typical f icgout = 8 mhz out of reset fbe ?fll bypassed external f ext / r na fei ?fll engaged internal (f irg / 7)* 64*n / r 64 typical f irg = 243 khz 4 n = 18 fee ?fll engaged external f ext * p * n / r range = 0 ; p = 64 range = 1; p = 1 4 <= n <= 18 1 <= r <= 128 table 6-6 mfd and rfd decode table mfd value multiplication factor (n) rfd division factor (r) 000 4 000 1 001 6 001 2 010 8 010 4 011 10 011 8 100 12 100 16 101 14 101 32 110 16 110 64 111 18 111 128 register bit 7 654321 bit 0 icgc1 0 range refs clks oscsten 0 (1) notes : 1. this bit is reserved for motorola internal use only. any write operations to this register should write a 0 to this bit. 0 icgc2 lolre mfd locre rfd icgs1 clkst refst lols lock locs ercs icgif icgs2 0 0 0 0 0 0 0 dcos icgfltu 0 0 0 0 flt icgfltl flt icgtrm trim = unimplemented or reserved
internal clock generator (icg) module mc9s08gb/gt 96 motorola 6.4.2 example #1: external crystal = 32 khz, bus frequency = 4.19 mhz in this example, the fll will be used (in fee mode) to multiply the external 32 khz oscillator up to 8.38-mhz to achieve 4.19 mhz bus frequency. after the mcu is released from reset, the icg is in self-clocked mode (scm) and supplies approximately 8 mhz on icgout, which corresponds to a 4 mhz bus frequency (f bus ). the clock scheme will be fll engaged, external (fee). so f icgout = f ext * p * n / r ; p = 64, f ext = 32 khz solving for n / r gives: n / r = 8.38 mhz /(32 khz * 64) = 4 ; we can choose n = 4 and r =1 the values needed in each register to set up the desired operation are: icgc1 = $38 (%00111000) bit 7 0 unimplemented or reserved, always reads zero bit 6 range 0 configures oscillator for low-frequency range; fll prescale factor is 64 bit 5 refs 1 oscillator using crystal or resonator is requested bits 4:3 clks 11 fll engaged, external reference clock mode bit 2 oscsten 0 oscillator disabled bit 1 0 reserved for motorola? internal use; always write zero bit 0 0 unimplemented or reserved, always reads zero icgc2 = $00 (%00000000) bit 7 lolre 0 generates an interrupt request on loss of lock bits 6:4 mfd 000 sets the mfd multiplication factor to 4 bit 3 locre 0 generates an interrupt request on loss of clock bits 2:0 rfd 000 sets the rfd division factor to 2 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only; should read dcos = 1 before performing any time critical tasks icgfltlu/l = $xx only needed in self-clocked mode; flt will be adjusted by loop to give 8.38 mhz dco clock bits 15:12 unused 0000 bits 11:0 flt no need for user initialization icgtrm = $xx bits 7:0 trim only need to write when trimming internal oscillator; not used when external crystal is clock source
data sheet ?mc9s08gb60/d v1.5 motorola 97 mc9s08gb/gt figure 6-8 shows flow charts for three conditions requiring icg initialization. figure 6-8 icg initialization for fee in example #1 reset continue recovery from stop check lock = 1? no yes fll lock status. initialize icg icg1 = $38 icg2 = $00 recovery from stop oscsten = 1 oscsten = 0 continue check lock = 1? no yes fll lock status. continue check lock = 1? no yes fll lock status. note: this will require the oscillator to start and stabilize. actual time is dependent on crystal /resonator and external circuitry. quick recovery from stop minimum current draw in stop
internal clock generator (icg) module mc9s08gb/gt 98 motorola 6.4.3 example #2: external crystal = 4 mhz, bus frequency = 20 mhz in this example, the fll will be used (in fee mode) to multiply the external 4 mhz oscillator up to 40-mhz to achieve 20 mhz bus frequency. after the mcu is released from reset, the icg is in self-clocked mode (scm) and supplies approximately 8 mhz on icgout which corresponds to a 4 mhz bus frequency (f bus ). during reset initialization software, the clock scheme will be set to fll engaged, external (fee). so f icgout = f ext * p * n / r ; p = 1, f ext = 4.00 mhz solving for n / r gives: n / r = 40 mhz /(4 mhz * 1) = 10 ; we can choose n = 10 and r = 1 the values needed in each register to set up the desired operation are: icgc1 = $78 (%01111000) bit 7 0 unimplemented or reserved, always reads zero bit 6 range 1 configures oscillator for high-frequency range; fll prescale factor is 1 bit 5 refs 1 requests an oscillator bits 4:3 clks 11 fll engaged, external reference clock mode bit 2 oscsten 0 disables the oscillator bit 1 0 reserved for motorola? internal use; always write zero bit 0 0 unimplemented or reserved, always reads zero icgc2 = $30 (%00110000) bit 7 lolre 0 generates an interrupt request on loss of lock bit 6:4 mfd 011 sets the mfd multiplication factor to 10 bit 3 locre 0 generates an interrupt request on loss of clock bit 2:0 rfd 000 sets the rfd division factor to 1 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only. should read dcos before performing any time critical tasks icgfltlu/l = $xx not used in this example icgtrm not used in this example
data sheet ?mc9s08gb60/d v1.5 motorola 99 mc9s08gb/gt figure 6-9 icg initialization and stop recovery for example #2 reset continue recovery check lock = 1? no yes fll lock status initialize icg icg1 = $7a icg2 = $30 continue check lock = 1? no yes fll lock status service interrupt source (f bus = 4 mhz) from stop
internal clock generator (icg) module mc9s08gb/gt 100 motorola 6.4.4 example #3: no external crystal connection, 5.4 mhz bus frequency in this example, the fll will be used (in fei mode) to multiply the internal 243 khz (approximate) reference clock up to 10.8 mhz to achieve 5.4 mhz bus frequency. this system will also use the trim function to fine tune the frequency based on an external reference signal. after the mcu is released from reset, the icg is in self-clocked mode (scm) and supplies approximately 8 mhz on icgout which corresponds to a 4 mhz bus frequency (f bus ). the clock scheme will be fll engaged, internal (fei). so f icgout = (f irg / 7) * p * n / r ; p = 64, f irg = 243 khz solving for n / r gives: n / r = 10.8 mhz /(243/7 khz * 64) = 4.86 ; we can choose n = 10 and r = 2. a trim procedure will be required to hone the frequency to exactly 5.4 mhz. an example of the trim procedure is shown in example #4. the values needed in each register to set up the desired operation are: icgc1 = $28 (%00101000) bit 7 0 unimplemented or reserved, always reads zero bit 6 range 0 configures oscillator for low-frequency range; fll prescale factor is 64 bit 5 refs 1 oscillator using crystal or resonator requested (bit is really a don? care) bits 4:3 clks 01 fll engaged, internal reference clock mode bit 2 oscsten 0 disables the oscillator bit 1 0 reserved for motorola? internal use; always write zero bit 0 0 unimplemented or reserved, always reads zero icgc2 = $31 (%00110001) bit 7 lolre 0 generates an interrupt request on loss of lock bit 6:4 mfd 011 sets the mfd multiplication factor to 10 bit 3 locre 0 generates an interrupt request on loss of clock bit 2:0 rfd 001 sets the rfd division factor to 2 icgs1 = $xx this is read only except for clearing interrupt flag icgs2 = $xx this is read only; good idea to read this before performing time critical operations icgfltlu/l = $xx not used in this example icgtrm = $xx bit 7:0 trim only need to write when trimming internal oscillator; done in separate operation (see example #4)
data sheet ?mc9s08gb60/d v1.5 motorola 101 mc9s08gb/gt figure 6-10 icg initialization and stop recovery for example #3 reset continue check lock = 1? no yes fll lock status. initialize icg icg1 = $28 icg2 = $31 recovery continue check lock = 1? no yes fll lock status. note: this will require the interal reference clock to start and stabilize. from stop
internal clock generator (icg) module mc9s08gb/gt 102 motorola 6.4.5 example #4: internal clock generator trim the internally generated clock source is guaranteed to have a period 25% of the nominal value. in some case this may be sufficient accuracy. for other applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. this section outlines one example of trimming the internal oscillator. many other possible trimming procedures are valid and can be used. figure 6-11 trim procedure in this particular case, the mcu has been attached to a pcb and the entire assembly is undergoing final test with automated test equipment. a separate signal or message is provided to the mcu operating under user provided software control. the mcu initiates a trim procedure as outlined in figure 6-11 while the tester supplies a precision reference signal. if the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using a reduction divisor (r) twice the final value. once the trim procedure is complete, the reduction divisor can be restored. this will prevent accidental overshoot of the maximum clock frequency. initial conditions: 1) clock supplied from ate has 500 sec duty period 2) icg configured for internal reference with 4 mhz bus start trim procedure continue case statement count < expected = 500 . measure incoming clock width icgtrm = $80, n = 1 count > expected = 500 count = expected = 500 store icgtrm value in non-volatile memory icgtrm = icgtrm = icgtrm - 128 / (2**n) icgtrm + 128 / (2**n) n = n + 1 (count = # of bus clocks / 4) (decreasing icgtrm increases the frequency) (increasing icgtrm decreases the frequency) no yes is n > 8? (running too slow) (running too fast)
data sheet ?mc9s08gb60/d v1.5 motorola 103 mc9s08gb/gt 6.5 icg registers and control bits refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all icg registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. 6.5.1 icg control register 1 (icgc1) figure 6-12 icg control register 1 (icgc1) range frequency range select the range bit controls the oscillator, reference divider, and fll loop prescaler multiplication factor (p). it selects one of two reference frequency ranges for the icg. the range bit is write-once after a reset. the range bit only has an effect in fll engaged external and fll bypassed external modes. 1 = oscillator configured for high frequency range. fll loop prescale factor p is 1. 0 = oscillator configured for low frequency range. fll loop prescale factor p is 64. refs external reference select the refs bit controls the external reference clock source for icgerclk. the refs bit is write-once after a reset. 1 = oscillator using crystal or resonator requested. 0 = external clock requested. clks clock mode select the clks bits control the clock mode according to table 6-7 . if fll bypassed external is requested, it will not be selected until ercs = 1. if the icg enters off mode, the clks bits will remain unchanged.writes to the clks bits will not take effect if a previous write is not complete. bit 7 654321 bit 0 read: 0 range refs clks oscsten 0 (1) notes : 1. this bit is reserved for motorola internal use only. any write operations to this register should write a 0 to this bit. 0 write: reset: 01000100 = unimplemented or reserved
internal clock generator (icg) module mc9s08gb/gt 104 motorola the clks bits are writable at any time, unless the first write after a reset was clks = 0x, the clks bits cannot be written to 1x until after the next reset (because the extal pin was not reserved). oscsten enable oscillator in off mode the oscsten bit controls whether or not the oscillator circuit remains enabled when the icg enters off mode. 1 = oscillator enabled when icg is in off mode, clks = 1x and refst = 1. 0 = oscillator disabled when icg is in off mode unless enable is high, clks = 10, and refst = 1. 6.5.2 icg control register 2 (icgc2) figure 6-13 icg control register 2 (icgc2) lolre loss of lock reset enable the lolre bit determines what type of request is made by the icg following a loss of lock indication. the lolre bit only has an effect when lols is set. 1 = generate a reset request on loss of lock. 0 = generate an interrupt request on loss of lock. mfd multiplication factor the mfd bits control the programmable multiplication factor in the fll loop. the value specified by the mfd bits establishes the multiplication factor (n) applied to the reference frequency. writes to the mfd bits will not take effect if a previous write is not complete. table 6-7 clks clock select clks[1:0] clock mode 00 self-clocked 01 fll engaged, internal reference 10 fll bypassed, external reference 11 fll engaged, external reference bit 7 654321 bit 0 read: lolre mfd locre rfd write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 105 mc9s08gb/gt locre loss of clock reset enable the locre bit determines how the system handles a loss of clock condition. 1 = generate a reset request on loss of clock. 0 = generate an interrupt request on loss of clock. rfd reduced frequency divider the rfd bits control the value of the divider following the clock select circuitry. the value specified by the rfd bits establishes the division factor (r) applied to the selected output clock source. writes to the rfd bits will not take effect if a previous write is not complete. table 6-8 mfd multiplication factor select mfd value multiplication factor (n) 000 4 001 6 010 8 011 10 100 12 101 14 110 16 111 18 table 6-9 rfd reduced frequency divider select rfd division factor (r) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128
internal clock generator (icg) module mc9s08gb/gt 106 motorola 6.5.3 icg status register 1 (icgs1) figure 6-14 icg status register 1 (icgs1) clkst clock mode status the clkst bits indicate the current clock mode. the clkst bits don? update immediately after a write to the clks bits due to internal synchronization between clock domains. refst reference clock status the refst bit indicates which clock reference is currently selected by the reference select circuit. 1 = crystal/resonator selected. 0 = external clock selected. lols fll loss of lock status the lols bit is a sticky indication of fll lock status. 1 = fll has unexpectedly lost lock since lols was last cleared, lolre determines action taken. 0 = fll has not unexpectedly lost lock since lols was last cleared. lock fll lock status the lock bit indicates whether the fll has acquired lock. the lock bit is cleared in off, self-clocked, and fll bypassed modes. 1 = fll is currently locked. 0 = fll is currently unlocked. bit 7 654321 bit 0 read: clkst refst lols lock locs ercs icgif write: 1 reset: 00000000 = unimplemented or reserved table 6-10 clkst clock mode status clkst[1:0] clock status 00 self-clocked 01 fll engaged, internal reference 10 fll bypassed, external reference 11 fll engaged, external reference
data sheet ?mc9s08gb60/d v1.5 motorola 107 mc9s08gb/gt locs loss of clock status the locs bit is an indication of icg loss of clock status. 1 = icg has lost clock since locs was last cleared, locre determines action taken. 0 = icg has not lost clock since locs was last cleared. ercs external reference clock status the ercs bit is an indication of whether or not the external reference clock (icgerclk) meets the minimum frequency requirement. 1 = external reference clock is stable, frequency requirement is met. 0 = external reference clock is not stable, frequency requirement is not met. icgif icg interrupt flag the icgif read/write flag is set when an icg interrupt request is pending. it is cleared by a reset or by reading the icg status register when icgif is set and then writing a logic 1 to icgif. if another icg interrupt occurs before the clearing sequence is complete, the sequence is reset so icgif would remain set after the clear sequence was completed for the earlier interrupt. writing a logic 0 to icgif has no effect. 1 = an icg interrupt request is pending. 0 = no icg interrupt request is pending. 6.5.4 icg status register 2 (icgs2) figure 6-15 icg status register 2 (icgs2) dcos dco clock stable the dcos bit is set when the dco clock (icg2dclk) is stable, meaning the count error has not changed by more than n unlock for two consecutive samples and the dco clock is not static. this bit is used when exiting off state if clks = x1 to determine when to switch to the requested clock mode. it is also used in self-clocked mode to determine when to start monitoring the dco clock. this bit is cleared upon entering the off state. 1 = dco clock is stable. 0 = dco clock is unstable. bit 7 654321 bit 0 read: 0000000 dcos write: reset: 00000000 = unimplemented or reserved
internal clock generator (icg) module mc9s08gb/gt 108 motorola 6.5.5 icg filter registers (icgfltu, icgfltl) figure 6-16 icg upper filter register (icgfltu) figure 6-17 icg lower filter register (icgfltl) the filter registers show the filter value (flt). flt filter value the flt bits indicate the current filter value, which controls the dco frequency. the flt bits are read only except when the clks bits are programmed to self-clocked mode (clks = 00). in self-clocked mode, any write to icgfltu updates the current 12-bit filter value. writes to the icgfltu register will not affect flt if a previous latch sequence is not complete. 6.5.6 icg trim register (icgtrm) figure 6-18 icg trim register (icgtrm) trim icg trim setting the trim bits control the internal reference generator frequency. they allow a 25% adjustment of the nominal (por) period. the bit? effect on period is binary weighted (i.e., bit 1 will adjust twice as much as changing bit 0). increasing the binary value in trim will increase the period and decreasing the value will decrease the period. bit 15 14 13 12 11 10 9 bit 8 read: 0000 flt write: reset: 00000000 = unimplemented or reserved bit 7 654321 bit 0 read: flt write: reset: 11000000 76543210 read: trim write: por: 10000000 reset: uuuuuuuu u = unaffected by mcu reset
data sheet ?mc9s08gb60/d v1.5 motorola 109 mc9s08gb/gt section 7 central processor unit (cpu) 7.1 introduction this section provides summary information about the registers, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1, motorola document order number hcs08rmv1/d. the hcs08 cpu is fully source- and object-code-compatible with the m68hc08 cpu. several instructions and enhanced addressing modes were added to improve c compiler efficiency and to support a new background debug system which replaces the monitor mode of earlier m68hc08 microcontrollers (mcu).
central processor unit (cpu) mc9s08gb/gt 110 motorola 7.2 features features of the hcs08 cpu include: object code fully upward-compatible with m68hc05 and m68hc08 families all registers and memory are mapped to a single 64-kbyte address space 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) 16-bit index register (h:x) with powerful indexed addressing modes 8-bit accumulator (a) many instructions treat x as a second general-purpose 8-bit register seven addressing modes: inherent ?operands in internal registers relative ?8-bit signed offset to branch destination immediate ?operand in next object code byte(s) direct ?operand in memory at $0000?00ff extended ?operand anywhere in 64-kbyte address space indexed relative to h:x ?five submodes including auto increment indexed relative to sp ?improves c efficiency dramatically memory-to-memory data move instructions with four address mode combinations overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations efficient bit manipulation instructions fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions stop and wait instructions to invoke low-power operating modes 7.3 programmer? model and cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map.
data sheet ?mc9s08gb60/d v1.5 motorola 111 mc9s08gb/gt figure 7-1 cpu registers 7.3.1 accumulator (a) the a accumulator is a general-purpose 8-bit register. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu results are often stored into the a accumulator after arithmetic and logical operations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of a can be stored to memory using various addressing modes to specify the address where data from a will be stored. reset has no effect on the contents of the a accumulator. 7.3.2 index register (h:x) this 16-bit register is actually two separate 8-bit registers (h and x) which often work together as a 16-bit address pointer where h holds the upper byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8-bit register which can be used to hold 8-bit data values. x can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or transferred to a where arithmetic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is forced to $00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz
central processor unit (cpu) mc9s08gb/gt 112 motorola 7.3.3 stack pointer (sp) this 16-bit address pointer register points at the next available location on the automatic last-in-first-out (lifo) stack. the stack may be located anywhere in the 64-kbyte address space which has ram and can be any size up to the amount of available ram. the stack is used to automatically save the return address for subroutine calls, the return address and cpu registers during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to $00ff at reset for compatibility with the earlier m68hc05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ram (from the end of the on-chip registers to $00ff). the rsp (reset stack pointer) instruction was included for compatibility with the m68hc05 family and is seldom used in new hcs08 programs because it only affects the low-order half of the stack pointer. 7.3.4 program counter (pc) the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. during normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. this is called a change-of-flow. during reset, the program counter is loaded with the reset vector which is located at $fffe and $ffff. the vector stored there is the address of the first instruction that will be executed after exiting the reset state. 7.3.5 condition code register (ccr) the 8-bit condition code register contains the interrupt mask (i) and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code bits in general terms. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1, motorola document order number hcs08rmv1/d.
data sheet ?mc9s08gb60/d v1.5 motorola 113 mc9s08gb/gt figure 7-2 condition code register v two? complement overflow flag the cpu sets the overflow flag when a two? complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i interrupt mask bit when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the first instruction of the interrupt service routine is executed. 1 = interrupts disabled 0 = interrupts enabled interrupts are not recognized at the instruction boundary after any instruction which clears i (cli or tap). this ensures that the next instruction after a cli or tap will always be executed without the possibility of an intervening interrupt, provided i was set. n negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most significant bit of the loaded or stored value was 1. 1 = negative result 0 = non-negative result condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow 70 ccr c v11hinz
central processor unit (cpu) mc9s08gb/gt 114 motorola z zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 or $0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 1 = zero result 0 = non-zero result c carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ?such as bit test and branch, shift, and rotate ?also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7.4 addressing modes addressing modes define the way the cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/output (i/o) ports share a single 64-kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access variables in ram can also be used to access i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. instructions such as brclr, brset, cbeq, and dbnz use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. for brclr, brset, cbeq, and dbnz, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.4.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 7.4.2 relative addressing mode (rel) relative addressing mode is used to specify the destination location for branch instructions. a signed 8-bit offset value is located in the memory location immediately following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter which causes program execution to continue at the branch destination address.
data sheet ?mc9s08gb60/d v1.5 motorola 115 mc9s08gb/gt 7.4.3 immediate addressing mode (imm) in immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. in the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 7.4.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page ($0000?00ff). during execution a 16-bit address is formed by concatenating an implied $00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. this is faster and more memory efficient than specifying a complete 16-bit address for the operand. 7.4.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.4.6 indexed addressing mode indexed addressing mode has seven variations including five which use the 16-bit h:x index register pair and two that use the stack pointer as the base reference. 7.4.6.1 indexed, no offset (ix) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 7.4.6.2 indexed, no offset with post increment (ix+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + $0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 7.4.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
central processor unit (cpu) mc9s08gb/gt 116 motorola the index register pair is then incremented (h:x = h:x + $0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 7.4.6.5 indexed, 16-bit offset (ix2) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.5 special operations the cpu performs a few special operations which are similar to instructions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop and wait directly affect other mcu circuitry. this section provides additional information about these operations. 7.5.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an external active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determines the source, refer to the resets, interrupts, and system configuration section. the reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from $fffe and $ffff and to fill the instruction queue in preparation for execution of the first program instruction. 7.5.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction which is where the cpu should return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started.
data sheet ?mc9s08gb60/d v1.5 motorola 117 mc9s08gb/gt the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routine. although it is possible to clear the i bit with an instruction in the interrupt service routine, this would allow nesting of interrupts which is not recommended because it leads to programs that are difficult to debug and maintain. for compatibility with the earlier m68hc05 mcus, the high-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt sequence. it is recommended that the user should use a pshh instruction at the beginning of the service routine to save h and then use a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certain that the interrupt service routine does not use any instructions or auto-increment addressing modes which might change the value of h. the software interrupt (swi) instruction is like a hardware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.5.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumption while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event occurs, the cpu clocks will resume and the interrupt or reset event will be processed normally. if a serial background command is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in wait mode. 7.5.4 stop mode operation usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. in such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be configured to keep a minimum set of
central processor unit (cpu) mc9s08gb/gt 118 motorola clocks running in stop mode. this optionally allows an internal periodic signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the background interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial background command is issued to the mcu through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode depends on the particular hcs08 and whether the oscillator was stopped in stop mode. refer to the modes chart in section 3 for more details. 7.5.5 bgnd instruction the bgnd instruction is new to the hcs08 compared to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to stop processing user instructions and enter the active background mode. the only way to resume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program reaches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program. 7.6 hcs08 instruction set summary instruction set summary nomenclature the nomenclature listed here is used in the instruction descriptions in table 7-1 . operators ( ) = contents of register or memory location shown inside parentheses = is loaded with (read: ?ets? & = boolean and | = boolean or = boolean exclusive-or = multiply = divide : = concatenate + = add = negate (twos complement)
data sheet ?mc9s08gb60/d v1.5 motorola 119 mc9s08gb/gt cpu registers a = accumulator ccr = condition code register h = index register, higher order (most signi?ant) 8 bits x = index register, lower order (least signi?ant) 8 bits pc = program counter pch = program counter, higher order (most signi?ant) 8 bits pcl = program counter, lower order (least signi?ant) 8 bits sp = stack pointer memory and addressing m= a memory location or absolute data, depending on addressing mode m:m + $0001= a 16-bit value in two consecutive memory locations. the higher-order (most signi?ant) 8 bits are located at the address of m, and the lower-order (least signi?ant) 8 bits are located at the next higher sequential address. condition code register (ccr) bits v = twos complement over?w indicator, bit 7 h = half carry, bit 4 i = interrupt mask, bit 3 n = negative indicator, bit 2 z = zero indicator, bit 1 c = carry/borrow, bit 0 (carry out of bit 7) ccr activity notation = bit not affected 0 = bit forced to 0 1 = bit forced to 1 = bit set or cleared according to results of operation u = unde?ed after the operation machine coding notation dd = low-order 8 bits of a direct address $0000?00ff (high byte assumed to be $00) ee = upper 8 bits of 16-bit offset ff = lower 8 bits of 16-bit offset or 8-bit offset ii = one byte of immediate data jj = high-order byte of a 16-bit immediate data value kk = low-order byte of a 16-bit immediate data value hh = high-order byte of 16-bit extended address ll = low-order byte of 16-bit extended address rr = relative offset
central processor unit (cpu) mc9s08gb/gt 120 motorola source form everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. the initial 3- to 5-letter mnemonic is always a literal expression. all commas, pound signs (#), parentheses, and plus signs (+) are literal characters. n any label or expression that evaluates to a single integer in the range 0? opr8i any label or expression that evaluates to an 8-bit immediate value opr16i any label or expression that evaluates to a 16-bit immediate value opr8a any label or expression that evaluates to an 8-bit value. the instruction treats this 8-bit value as the low order 8 bits of an address in the direct page of the 64-kbyte address space ($00xx). opr16a any label or expression that evaluates to a 16-bit value. the instruction treats this value as an address in the 64-kbyte address space. oprx8 any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing oprx16 any label or expression that evaluates to a 16-bit value. since the hcs08 has a 16-bit address bus, this can be either a signed or an unsigned value. rel any label or expression that refers to an address that is within ?28 to + 127 locations from the next address after the last byte of object code for the current instruction. the assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. address modes inh = inherent (no operands) imm = 8-bit or 16-bit immediate dir = 8-bit direct ext = 16-bit extended ix = 16-bit indexed no offset ix+ = 16-bit indexed no offset, post increment (cbeq and mov only) ix1 = 16-bit indexed with 8-bit offset from h:x ix1+ = 16-bit indexed with 8-bit offset, post increment (cbeq only) ix2 = 16-bit indexed with 16-bit offset from h:x rel = 8-bit relative offset sp1 = stack pointer with 8-bit offset sp2 = stack pointer with 16-bit offset
data sheet ?mc9s08gb60/d v1.5 motorola 121 mc9s08gb/gt table 7-1 hcs08 instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand bus cycles (1) vh i nzc adc # opr8i adc opr8a adc opr16a adc oprx16 ,x adc oprx8 ,x adc ,x adc oprx16 ,sp adc oprx8 ,sp add with carry a (a) + (m) + (c) imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9ed9 9ee9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 add # opr8i add opr8a add opr16a add oprx16 ,x add oprx8 ,x add ,x add oprx16 ,sp add oprx8 ,sp add without carry a (a) + (m) imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9edb 9eeb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ais # opr8i add immediate value (signed) to stack pointer sp (sp) + (m) m is sign extended to a 16-bit value imm a7 ii 2 aix # opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) m is sign extended to a 16-bit value imm af ii 2 and # opr8i and opr8a and opr16a and oprx16 ,x and oprx8 ,x and ,x and oprx16 ,sp and oprx8 ,sp logical and a (a) & (m) 0 imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9ed4 9ee4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 asl opr8a asla aslx asl oprx8 ,x asl ,x asl oprx8 ,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 5 1 1 5 4 6 asr opr8a asra asrx asr oprx8 ,x asr ,x asr oprx8 ,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 5 1 1 5 4 6 bcc rel branch if carry bit clear branch if (c) = 0 rel 24 rr 3 bclr n , opr8a clear bit n in memory mn 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) branch if (c) = 1 rel 25 rr 3 beq rel branch if equal branch if (z) = 1 rel 27 rr 3 bge rel branch if greater than or equal to (signed operands) branch if (n v ) = 0 rel 90 rr 3 bgnd enter active background if enbdm = 1 waits for and processes bdm commands until go, trace1, or taggo inh 82 5+ bgt rel branch if greater than (signed operands) branch if (z) | (n v ) = 0 rel 92 rr 3 bhcc rel branch if half carry bit clear branch if (h) = 0 rel 28 rr 3 c b0 b7 0 b0 b7 c
central processor unit (cpu) mc9s08gb/gt 122 motorola bhcs rel branch if half carry bit set branch if (h) = 1 rel 29 rr 3 bhi rel branch if higher branch if (c) | (z) = 0 rel 22 rr 3 bhs rel branch if higher or same (same as bcc) branch if (c) = 0 rel 24 rr 3 bih rel branch if irq pin high branch if irq pin = 1 rel 2f rr 3 bil rel branch if irq pin low branch if irq pin = 0 rel 2e rr 3 bit # opr8i bit opr8a bit opr16a bit oprx16 ,x bit oprx8 ,x bit ,x bit oprx16 ,sp bit oprx8 ,sp bit test (a) & (m) (ccr updated but operands not changed) 0 imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9ed5 9ee5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ble rel branch if less than or equal to (signed operands) branch if (z) | (n v ) = 1 rel 93 rr 3 blo rel branch if lower (same as bcs) branch if (c) = 1 rel 25 rr 3 bls rel branch if lower or same branch if (c) | (z) = 1 rel 23 rr 3 blt rel branch if less than (signed operands) branch if (n v ) = 1 rel 91 rr 3 bmc rel branch if interrupt mask clear branch if (i) = 0 rel 2c rr 3 bmi rel branch if minus branch if (n) = 1 rel 2b rr 3 bms rel branch if interrupt mask set branch if (i) = 1 rel 2d rr 3 bne rel branch if not equal branch if (z) = 0 rel 26 rr 3 bpl rel branch if plus branch if (n) = 0 rel 2a rr 3 bra rel branch always no test rel 20 rr 3 brclr n , opr8a , rel branch if bit n in memory clear branch if (mn) = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never uses 3 bus cycles rel 21 rr 3 brset n , opr8a , rel branch if bit n in memory set branch if (mn) = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr8a set bit n in memory mn 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + $0002 push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 pc (pc) + rel rel ad rr 5 table 7-1 hcs08 instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand bus cycles (1) vh i nzc
data sheet ?mc9s08gb60/d v1.5 motorola 123 mc9s08gb/gt cbeq opr8a , rel cbeqa # opr8i , rel cbeqx # opr8i , rel cbeq oprx8 ,x+, rel cbeq ,x+, rel cbeq oprx8 ,sp, rel compare and branch if equal branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 clc clear carry bit c 0 0 inh 98 1 cli clear interrupt mask bit i 0 0 inh 9a 1 clr opr8a clra clrx clrh clr oprx8 ,x clr ,x clr oprx8 ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 001 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 5 1 1 1 5 4 6 cmp # opr8i cmp opr8a cmp opr16a cmp oprx16 ,x cmp oprx8 ,x cmp ,x cmp oprx16 ,sp cmp oprx8 ,sp compare accumulator with memory (a) ?(m) (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9ed1 9ee1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 com opr8a coma comx com oprx8 ,x com ,x com oprx8 ,sp complement (one? complement) m ( m)= $ff ?(m) a ( a) = $ff ?(a) x ( x) = $ff ?(x) m ( m) = $ff ?(m) m ( m) = $ff ?(m) m ( m) = $ff ?(m) 0 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 5 1 1 5 4 6 cphx opr16a cphx # opr16i cphx opr8a cphx oprx8 ,sp compare index register (h:x) with memory (h:x) ?(m:m + $0001) (ccr updated but operands not changed) ext imm dir sp1 3e 65 75 9ef3 hh ll jj kk dd ff 6 3 5 6 cpx # opr8i cpx opr8a cpx opr16a cpx oprx16 ,x cpx oprx8 ,x cpx ,x cpx oprx16 ,sp cpx oprx8 ,sp compare x (index register low) with memory (x) ?(m) (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9ed3 9ee3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 daa decimal adjust accumulator after add or adc of bcd values (a) 10 u inh 72 1 dbnz opr8a , rel dbnza rel dbnzx rel dbnz oprx8 ,x, rel dbnz ,x, rel dbnz oprx8 ,sp, rel decrement and branch if not zero decrement a, x, or m branch if (result) 0 dbnzx affects x not h dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 dec opr8a deca decx dec oprx8 ,x dec ,x dec oprx8 ,sp decrement m (m) ?$01 a (a) ?$01 x (x) ?$01 m (m) ?$01 m (m) ?$01 m (m) ?$01 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 5 1 1 5 4 6 div divide a (h:a) (x) h remainder inh 52 6 table 7-1 hcs08 instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand bus cycles (1) vh i nzc
central processor unit (cpu) mc9s08gb/gt 124 motorola eor # opr8i eor opr8a eor opr16a eor oprx16 ,x eor oprx8 ,x eor ,x eor oprx16 ,sp eor oprx8 ,sp exclusive or memory with accumulator a (a m) 0 imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9ed8 9ee8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 inc opr8a inca incx inc oprx8 ,x inc ,x inc oprx8 ,sp increment m (m) + $01 a (a) + $01 x (x) + $01 m (m) + $01 m (m) + $01 m (m) + $01 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 5 1 1 5 4 6 jmp opr8a jmp opr16a jmp oprx16 ,x jmp oprx8 ,x jmp ,x jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 jsr opr8a jsr opr16a jsr oprx16 ,x jsr oprx8 ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 pc unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 lda # opr8i lda opr8a lda opr16a lda oprx16 ,x lda oprx8 ,x lda ,x lda oprx16 ,sp lda oprx8 ,sp load accumulator from memory a (m) 0 imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9ed6 9ee6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ldhx # opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16 ,x ldhx oprx8 ,x ldhx oprx8 ,sp load index register (h:x) from memory h:x ( m:m + $0001 ) 0 imm dir ext ix ix2 ix1 sp1 45 55 32 9eae 9ebe 9ece 9efe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 ldx # opr8i ldx opr8a ldx opr16a ldx oprx16 ,x ldx oprx8 ,x ldx ,x ldx oprx16 ,sp ldx oprx8 ,sp load x (index register low) from memory x (m) 0 imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9ede 9eee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 lsl opr8a lsla lslx lsl oprx8 ,x lsl ,x lsl oprx8 ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 5 1 1 5 4 6 lsr opr8a lsra lsr x lsr oprx8 ,x lsr ,x lsr oprx8 ,sp logical shift right 0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 5 1 1 5 4 6 mov opr8a , opr8a mov opr8a ,x+ mov # opr8i , opr8a mov ,x+, opr8a move (m) destination (m) source h:x (h:x) + $0001 in ix+/dir and dir/ix+ modes 0 dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 mul unsigned multiply x:a (x) (a) 0 0 inh 42 5 table 7-1 hcs08 instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand bus cycles (1) vh i nzc c b0 b7 0 b0 b7 c 0
data sheet ?mc9s08gb60/d v1.5 motorola 125 mc9s08gb/gt neg opr8a nega negx neg oprx8 ,x neg ,x neg oprx8 ,sp negate (two? complement) m ?(m) = $00 ?(m) a ?(a) = $00 ?(a) x ?(x) = $00 ?(x) m ?(m) = $00 ?(m) m ?(m) = $00 ?(m) m ?(m) = $00 ?(m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 5 1 1 5 4 6 nop no operation uses 1 bus cycle inh 9d 1 nsa nibble swap accumulator a (a[3:0]:a[7:4]) inh 62 1 ora # opr8i ora opr8a ora opr16a ora oprx16 ,x ora oprx8 ,x ora ,x ora oprx16 ,sp ora oprx8 ,sp inclusive or accumulator and memory a (a) | (m) 0 imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9eda 9eea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 psha push accumulator onto stack push (a); sp (sp ) $0001 inh 87 2 pshh push h (index register high) onto stack push (h) ; sp (sp ) $0001 inh 8b 2 pshx push x (index register low) onto stack push (x) ; sp (sp ) $0001 inh 89 2 pula pull accumulator from stack sp (sp + $0001); pull ( a ) inh 86 3 pulh pull h (index register high) from stack sp (sp + $0001); pull ( h ) inh 8a 3 pulx pull x (index register low) from stack sp (sp + $0001); pull ( x ) inh 88 3 rol opr8a rola rolx rol oprx8 ,x rol ,x rol oprx8 ,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 5 1 1 5 4 6 ror opr8a rora rorx ror oprx8 ,x ror ,x ror oprx8 ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 5 1 1 5 4 6 rsp reset stack pointer sp $ff (high byte not affected) inh 9c 1 rti return from interrupt sp (sp) + $0001; pull (ccr) sp (sp) + $0001; pull (a) sp (sp) + $0001; pull (x) sp (sp) + $0001; pull (pch) sp (sp) + $0001; pull (pcl) inh 80 9 rts return from subroutine sp sp + $0001 ; pull ( pch) sp sp + $0001; pull (pcl) inh 81 6 sbc # opr8i sbc opr8a sbc opr16a sbc oprx16 ,x sbc oprx8 ,x sbc ,x sbc oprx16 ,sp sbc oprx8 ,sp subtract with carry a (a) ?(m) ?(c) imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9ed2 9ee2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 sec set carry bit c 1 1 inh 99 1 sei set interrupt mask bit i 1 1 inh 9b 1 table 7-1 hcs08 instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand bus cycles (1) vh i nzc c b0 b7 b0 b7 c
central processor unit (cpu) mc9s08gb/gt 126 motorola sta opr8a sta opr16a sta oprx16 ,x sta oprx8 ,x sta ,x sta oprx16 ,sp sta oprx8 ,sp store accumulator in memory m (a) 0 dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9ed7 9ee7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 sthx opr8a sthx opr16a sthx oprx8 ,sp store h:x (index reg.) (m:m + $0001) (h:x) 0 dir ext sp1 35 96 9eff dd hh ll ff 4 5 5 stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing 0 inh 8e 2+ stx opr8a stx opr16a stx oprx16 ,x stx oprx8 ,x stx ,x stx oprx16 ,sp stx oprx8 ,sp store x (low 8 bits of index register) in memory m (x) 0 dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9edf 9eef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 sub # opr8i sub opr8a sub opr16a sub oprx16 ,x sub oprx8 ,x sub ,x sub oprx16 ,sp sub oprx8 ,sp subtract a (a) (m) imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9ed0 9ee0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 swi software interrupt pc (pc) + $0001 push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 push (x); sp (sp) ?$0001 push (a); sp (sp) ?$0001 push (ccr); sp (sp) ?$0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte 1 inh 83 11 tap transfer accumulator to ccr ccr (a) inh 84 1 tax transfer accumulator to x (index register low) x (a) inh 97 1 tpa transfer ccr to accumulator a (ccr) inh 85 1 tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8 ,sp test for negative or zero (m) ?$00 (a) ?$00 (x) ?$00 (m) ?$00 (m) ?$00 (m) ?$00 0 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 4 1 1 4 3 5 tsx transfer sp to index reg. h:x (sp) + $0001 inh 95 2 txa transfer x (index reg. low) to accumulator a (x) inh 9f 1 txs transfer index reg. to sp sp (h:x) ?$0001 inh 94 2 wait enable interrupts; wait for interrupt i bit 0; halt cpu 0 inh 8f 2+ notes : 1. bus clock frequency is one-half of the cpu clock frequency. table 7-1 hcs08 instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand bus cycles (1) vh i nzc
data sheet ?mc9s08gb60/d v1.5 motorola 127 mc9s08gb/gt table 7-2 opcode map (sheet 1 of 2) bit-manipulation branch read-modify-write control register/memory 00 5 brset0 3 dir 10 5 bset0 2 dir 20 3 bra 2 rel 30 5 neg 2 dir 40 1 nega 1 inh 50 1 negx 1 inh 60 5 neg 2 ix1 70 4 neg 1ix 80 9 rti 1 inh 90 3 bge 2 rel a0 2 sub 2 imm b0 3 sub 2 dir c0 4 sub 3 ext d0 4 sub 3 ix2 e0 3 sub 2 ix1 f0 3 sub 1ix 01 5 brclr0 3 dir 11 5 bclr0 2 dir 21 3 brn 2 rel 31 5 cbeq 3 dir 41 4 cbeqa 3 imm 51 4 cbeqx 3 imm 61 5 cbeq 3 ix1+ 71 5 cbeq 2 ix+ 81 6 rts 1 inh 91 3 blt 2 rel a1 2 cmp 2 imm b1 3 cmp 2 dir c1 4 cmp 3 ext d1 4 cmp 3 ix2 e1 3 cmp 2 ix1 f1 3 cmp 1ix 02 5 brset1 3 dir 12 5 bset1 2 dir 22 3 bhi 2 rel 32 5 ldhx 3 ext 42 5 mul 1 inh 52 6 div 1 inh 62 1 nsa 1 inh 72 1 daa 1 inh 82 5+ bgnd 1 inh 92 3 bgt 2 rel a2 2 sbc 2 imm b2 3 sbc 2 dir c2 4 sbc 3 ext d2 4 sbc 3 ix2 e2 3 sbc 2 ix1 f2 3 sbc 1ix 03 5 brclr1 3 dir 13 5 bclr1 2 dir 23 3 bls 2 rel 33 5 com 2 dir 43 1 coma 1 inh 53 1 comx 1 inh 63 5 com 2 ix1 73 4 com 1ix 83 11 swi 1 inh 93 3 ble 2 rel a3 2 cpx 2 imm b3 3 cpx 2 dir c3 4 cpx 3 ext d3 4 cpx 3 ix2 e3 3 cpx 2 ix1 f3 3 cpx 1ix 04 5 brset2 3 dir 14 5 bset2 2 dir 24 3 bcc 2 rel 34 5 lsr 2 dir 44 1 lsra 1 inh 54 1 lsrx 1 inh 64 5 lsr 2 ix1 74 4 lsr 1ix 84 1 ta p 1 inh 94 2 txs 1 inh a4 2 and 2 imm b4 3 and 2 dir c4 4 and 3 ext d4 4 and 3 ix2 e4 3 and 2 ix1 f4 3 and 1ix 05 5 brclr2 3 dir 15 5 bclr2 2 dir 25 3 bcs 2 rel 35 4 sthx 2 dir 45 3 ldhx 3 imm 55 4 ldhx 2 dir 65 3 cphx 3 imm 75 5 cphx 2 dir 85 1 tpa 1 inh 95 2 tsx 1 inh a5 2 bit 2 imm b5 3 bit 2 dir c5 4 bit 3 ext d5 4 bit 3 ix2 e5 3 bit 2 ix1 f5 3 bit 1ix 06 5 brset3 3 dir 16 5 bset3 2 dir 26 3 bne 2 rel 36 5 ror 2 dir 46 1 rora 1 inh 56 1 rorx 1 inh 66 5 ror 2 ix1 76 4 ror 1ix 86 3 pula 1 inh 96 5 sthx 3 ext a6 2 lda 2 imm b6 3 lda 2 dir c6 4 lda 3 ext d6 4 lda 3 ix2 e6 3 lda 2 ix1 f6 3 lda 1ix 07 5 brclr3 3 dir 17 5 bclr3 2 dir 27 3 beq 2 rel 37 5 asr 2 dir 47 1 asra 1 inh 57 1 asrx 1 inh 67 5 asr 2 ix1 77 4 asr 1ix 87 2 psha 1 inh 97 1 ta x 1 inh a7 2 ais 2 imm b7 3 sta 2 dir c7 4 sta 3 ext d7 4 sta 3 ix2 e7 3 sta 2 ix1 f7 2 sta 1ix 08 5 brset4 3 dir 18 5 bset4 2 dir 28 3 bhcc 2 rel 38 5 lsl 2 dir 48 1 lsla 1 inh 58 1 lslx 1 inh 68 5 lsl 2 ix1 78 4 lsl 1ix 88 3 pulx 1 inh 98 1 clc 1 inh a8 2 eor 2 imm b8 3 eor 2 dir c8 4 eor 3 ext d8 4 eor 3 ix2 e8 3 eor 2 ix1 f8 3 eor 1ix 09 5 brclr4 3 dir 19 5 bclr4 2 dir 29 3 bhcs 2 rel 39 5 rol 2 dir 49 1 rola 1 inh 59 1 rolx 1 inh 69 5 rol 2 ix1 79 4 rol 1ix 89 2 pshx 1 inh 99 1 sec 1 inh a9 2 adc 2 imm b9 3 adc 2 dir c9 4 adc 3 ext d9 4 adc 3 ix2 e9 3 adc 2 ix1 f9 3 adc 1ix 0a 5 brset5 3 dir 1a 5 bset5 2 dir 2a 3 bpl 2 rel 3a 5 dec 2 dir 4a 1 deca 1 inh 5a 1 decx 1 inh 6a 5 dec 2 ix1 7a 4 dec 1ix 8a 3 pulh 1 inh 9a 1 cli 1 inh aa 2 ora 2 imm ba 3 ora 2 dir ca 4 ora 3 ext da 4 ora 3 ix2 ea 3 ora 2 ix1 fa 3 ora 1ix 0b 5 brclr5 3 dir 1b 5 bclr5 2 dir 2b 3 bmi 2 rel 3b 7 dbnz 3 dir 4b 4 dbnza 2 inh 5b 4 dbnzx 2 inh 6b 7 dbnz 3 ix1 7b 6 dbnz 2ix 8b 2 pshh 1 inh 9b 1 sei 1 inh ab 2 add 2 imm bb 3 add 2 dir cb 4 add 3 ext db 4 add 3 ix2 eb 3 add 2 ix1 fb 3 add 1ix 0c 5 brset6 3 dir 1c 5 bset6 2 dir 2c 3 bmc 2 rel 3c 5 inc 2 dir 4c 1 inca 1 inh 5c 1 incx 1 inh 6c 5 inc 2 ix1 7c 4 inc 1ix 8c 1 clrh 1 inh 9c 1 rsp 1 inh bc 3 jmp 2 dir cc 4 jmp 3 ext dc 4 jmp 3 ix2 ec 3 jmp 2 ix1 fc 3 jmp 1ix 0d 5 brclr6 3 dir 1d 5 bclr6 2 dir 2d 3 bms 2 rel 3d 4 tst 2 dir 4d 1 tsta 1 inh 5d 1 tstx 1 inh 6d 4 tst 2 ix1 7d 3 tst 1ix 9d 1 nop 1 inh ad 5 bsr 2 rel bd 5 jsr 2 dir cd 6 jsr 3 ext dd 6 jsr 3 ix2 ed 5 jsr 2 ix1 fd 5 jsr 1ix 0e 5 brset7 3 dir 1e 5 bset7 2 dir 2e 3 bil 2 rel 3e 6 cphx 3 ext 4e 6 mov 3dd 5e 5 mov 2 dix+ 6e 4 mov 3 imd 7e 5 mov 2 ix+d 8e 2+ stop 1 inh 9e page 2 ae 2 ldx 2 imm be 3 ldx 2 dir ce 4 ldx 3 ext de 4 ldx 3 ix2 ee 3 ldx 2 ix1 fe 3 ldx 1ix 0f 5 brclr7 3 dir 1f 5 bclr7 2 dir 2f 3 bih 2 rel 3f 5 clr 2 dir 4f 1 clra 1 inh 5f 1 clrx 1 inh 6f 5 clr 2 ix1 7f 4 clr 1ix 8f 2+ wait 1 inh 9f 1 txa 1 inh af 2 aix 2 imm bf 3 stx 2 dir cf 4 stx 3 ext df 4 stx 3 ix2 ef 3 stx 2 ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode
central processor unit (cpu) mc9s08gb/gt 128 motorola bit-manipulation branch read-modify-write control register/memory 9e60 6 neg 3 sp1 9ed0 5 sub 4 sp2 9ee0 4 sub 3 sp1 9e61 6 cbeq 4 sp1 9ed1 5 cmp 4 sp2 9ee1 4 cmp 3 sp1 9ed2 5 sbc 4 sp2 9ee2 4 sbc 3 sp1 9e63 6 com 3 sp1 9ed3 5 cpx 4 sp2 9ee3 4 cpx 3 sp1 9ef3 6 cphx 3 sp1 9e64 6 lsr 3 sp1 9ed4 5 and 4 sp2 9ee4 4 and 3 sp1 9ed5 5 bit 4 sp2 9ee5 4 bit 3 sp1 9e66 6 ror 3 sp1 9ed6 5 lda 4 sp2 9ee6 4 lda 3 sp1 9e67 6 asr 3 sp1 9ed7 5 sta 4 sp2 9ee7 4 sta 3 sp1 9e68 6 lsl 3 sp1 9ed8 5 eor 4 sp2 9ee8 4 eor 3 sp1 9e69 6 rol 3 sp1 9ed9 5 adc 4 sp2 9ee9 4 adc 3 sp1 9e6a 6 dec 3 sp1 9eda 5 ora 4 sp2 9eea 4 ora 3 sp1 9e6b 8 dbnz 4 sp1 9edb 5 add 4 sp2 9eeb 4 add 3 sp1 9e6c 6 inc 3 sp1 9e6d 5 tst 3 sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4 ix2 9ece 5 ldhx 3 ix1 9ede 5 ldx 4 sp2 9eee 4 ldx 3 sp1 9efe 5 ldhx 3 sp1 9e6f 6 clr 3 sp1 9edf 5 stx 4 sp2 9eef 4 stx 3 sp1 9eff 5 sthx 3 sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3 sp1 hcs08 cycles instruction mnemonic addressing mode table 7-2 opcode map (sheet 2 of 2)
data sheet ?mc9s08gb60/d v1.5 motorola 129 mc9s08gb/gt section 8 parallel input/output 8.1 introduction this section explains software controls related to parallel input/output (i/o). the mc9s08gbxx has seven i/o ports which include a total of 56 general-purpose i/o pins (one of these pins is output only). the mc9s08gtxx has six i/o ports which include a total of up to 36 general-purpose i/o pins (one pin, ptg0, is output only). see the pins and connections section for more information about the logic and hardware aspects of these pins. many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or keyboard interrupts. when these other modules are not controlling the port pins, they revert to general-purpose i/o control. for each i/o pin, a port data bit provides access to input (read) and output (write) data, a data direction bit controls the direction of the pin, and a pullup enable bit enables an internal pullup device (provided the pin is configured as an input), and a slew rate control bit controls the rise and fall times of the pins. note: not all general-purpose i/o pins are available on all packages. to avoid extra current drain from floating input pins, the user? reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float.
parallel input/output mc9s08gb/gt 130 motorola figure 8-1 block diagram highlighting parallel input/output pins ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5
data sheet ?mc9s08gb60/d v1.5 motorola 131 mc9s08gb/gt 8.2 features parallel i/o features, depending on package choice, include: a total of 56 general-purpose i/o pins in seven ports (one is output only) high-current drivers on port c and port f pins hysteresis input buffers software-controlled pullups on each input pin software-controlled slew rate output buffers eight port a pins shared with kbi eight port b pins shared with atd eight high-current port c pins shared with sci2 and iic eight port d pins shared with tpm1 and tpm2 eight port e pins shared with sci1 and spi eight high-current port f pins eight port g pins shared with extal, xtal, and bkgd/ms 8.3 pin descriptions the mc9s08gb/gt has a total of 56 parallel i/o pins (one is output only) in seven 8-bit ports (pta?tg). not all pins are bonded out in all packages. consult the pin assignment in the pins and connections section for available parallel i/o pins. all of these pins are available for general-purpose i/o when they are not used by other on-chip peripheral systems. after reset, bkgd/ms is enabled and therefore is not usable as an output pin until bkgdpe in sopt is cleared. the rest of the peripheral functions are disabled. after reset, all data direction and pullup enable controls are set to 0s. these pins default to being high-impedance inputs with on-chip pullup devices disabled. the following paragraphs discuss each port and the software controls that determine each pin? use. 8.3.1 port a and keyboard interrupts figure 8-2 port a pin names port a is an 8-bit port shared among the kbi keyboard interrupt inputs and general-purpose i/o. any pins enabled as kbi inputs will be forced to act as inputs. port a bit 7 654321 bit 0 mcu pin: pta7/ kbip7 pta6/ kbip6 pta5/ kbip5 pta4/ kbip4 pta3/ kbip3 pta2/ kbip2 pta1/ kbip1 pta0/ kbip0
parallel input/output mc9s08gb/gt 132 motorola port a pins are available as general-purpose i/o pins controlled by the port a data (ptad), data direction (ptadd), pullup enable (ptape) and slew rate control (ptase) registers. refer to 8.4 parallel i/o controls for more information about general-pupose i/o control. port a can be configured to be keyboard interrupt input pins. refer to the keyboard interrupt (kbi) module section for more information about using port a pins as keyboard interrupts pins. 8.3.2 port b and analog to digital converter inputs figure 8-3 port b pin names port b is an 8-bit port shared among the atd inputs and general-purpose i/o. any pin enabled as atd inputs will be forced to act as inputs. port b pins are available as general-purpose i/o pins controlled by the port b data (ptbd), data direction (ptbdd), pullup enable (ptbpe), and slew rate control (ptbse) registers. refer to 8.4 parallel i/o controls for more information about general-pupose i/o control. when the atd module is enabled, analog pin enables are used to specify which pins on port b will be used as atd inputs. refer to the analog-to-digital converter (atd) module section for more information about using port b as a atd pins. 8.3.3 port c and sci2, iic, and high-current drivers figure 8-4 port c pin names port c is an 8-bit port which is shared among the sci2 and iic modules, and general-purpose i/o. when sci2 or iic modules are enabled the pin direction will be controlled by the module or function. port c has high current output drivers. port c pins are available as general-purpose i/o pins controlled by the port c data (ptcd), data direction (ptcdd), pullup enable (ptcpe) and slew rate control (ptcse) registers. refer to 8.4 parallel i/o controls for more information about general-pupose i/o control. when the sci2 module is enabled, ptc0 serves as the sci2 module? transmit pin (txd2) and ptc1 serves as the receive pin (rxd2). refer to the serial communications interface (sci) module section for more information about using ptc0 and ptc1 as sci pins port b bit 7 654321 bit 0 mcu pin: ptb7/ ad7 ptb6/ ad6 ptb5/ ad5 ptb4/ ad4 ptb3/ ad3 ptb2/ ad2 ptb1/ ad1 ptb0/ ad0 port c bit 7 653321 bit 0 mcu pin: ptc7 ptc6 ptc5 ptc4 ptc3/ scl ptc2/ sda ptc1/ rxd2 ptc0/ txd2
data sheet ?mc9s08gb60/d v1.5 motorola 133 mc9s08gb/gt when the iic module is enabled, ptc2 serves as the iic modules? serial data input/output pin (sda) and ptc3 serves as the clock pin (scl). refer to the inter-integrated circuit (iic) module section for more information about using ptc2 and ptc3 as iic pins. 8.3.4 port d, tpm1 and tpm2 figure 8-5 port d pin names port d is an 8-bit port shared with the two tpm modules, tpm1 and tpm2 and general-purpose i/o. when the tpm1 or tpm2 modules are enabled in output compare or input captures modes of operation, the pin direction will be controlled by the module function. port d pins are available as general-purpose i/o pins controlled by the port d data (ptdd), data direction (ptddd), pullup enable (ptdpe), and slew rate control (ptdse) registers. refer to 8.4 parallel i/o controls for more information about general-pupose i/o control. the tpm2 module can be configured to use ptd7?td3 as either input capture, output compare, pwm, or external clock input pins (ptd3 only). refer to the timer/pwm (tpm) module section for more information about using ptd7?td3 as timer pins. the tpm1 module can be configured to use ptd2?td0 as either input capture, output compare, pwm, or external clock input pins (ptd0 only). refer to the timer/pwm (tpm) module section for more information about using ptd2?td0 as timer pins. 8.3.5 port e, sci1, and spi figure 8-6 port e pin names port e is an 8-bit port shared with the sci1 module, spi module, and general-purpose i/o. when the sci or spi modules are enabled, the pin direction will be controlled by the module function. port e pins are available as general-purpose i/o pins controlled by the port e data (pted), data direction (ptedd), pullup enable (ptepe) and slew rate control (ptese) registers. refer to 8.4 parallel i/o controls for more information about general-pupose i/o control. when the sci1 module is enabled, pte0 serves as the sci1 module? transmit pin (txd1) and pte1 serves as the receive pin (rxd1). refer to the serial communications interface (sci) module section for more information about using pte0 and pte1 as sci pins. port d bit 7 654321 bit 0 mcu pin: ptd7/ tpm2ch4 ptd6/ tpm2ch3 ptd5/ tpm2ch2 ptd4/ tpm2ch1 ptd3/ tpm2ch0 ptd2/ tpm1ch2 ptd1/ tpm1ch1 ptd0/ tpm1ch0 port e bit 7 654321 bit 0 mcu pin: pte7 pte6 pte5/ spsck pte4/ mosi pte3/ miso pte2/ ss pte1/ rxd1 pte0/ txd1
parallel input/output mc9s08gb/gt 134 motorola when the spi module is enabled, pte2 serves as the spi module? slave select pin ( ss), pte3 serves as the master-in slave-out pin (miso), pte4 serves as the master-out slave-in pin (mosi), and pte5 serves as the spi clock pin (spsck). refer to the serial peripheral interface (spi) module section for more information about using pte5?te2 as spi pins. 8.3.6 port f and high-current drivers figure 8-7 port f pin names port f is an 8-bit port general-purpose i/o that is not shared with any peripheral module. port f has high current output drivers. port f pins are available as general-purpose i/o pins controlled by the port f data (ptfd), data direction (ptfdd), pullup enable (ptfpe), and slew rate control (ptfse) registers. refer to 8.4 parallel i/o controls for more information about general-pupose i/o control. 8.3.7 port g, bkgd/ms, and oscillator figure 8-8 port g pin names port g is an 8-bit port which is shared among the background/mode select function, oscillator, and general-purpose i/o. when the background/mode select function or oscillator is enabled, the pin direction will be controlled by the module function. port g pins are available as general-purpose i/o pins controlled by the port g data (ptgd), data direction (ptgdd), pullup enable (ptgpe), and slew rate control (ptgse) registers. refer to 8.4 parallel i/o controls for more information about general-pupose i/o control. the internal pullup for ptg0 is enabled when the background/mode select function is enabled, regardless of the state of ptgpe0. during reset, the bkgd/ms pin functions as a mode select pin. once the mcu is out of reset, the bkgd/ms pin becomes the background communications input/output pin. the ptg0 can be configured to be a general-purpose output pin. refer to the modes of operation section, the resets, interrupts, and system configuration section, and the development support section for more information about using this pin. the icg module can be configured to use ptg2?tg1 ports as crystal oscillator or external clock pins. refer to the internal clock generator (icg) module section for more information about using these pins as oscillator pins. port f bit 7 654321 bit 0 mcu pin: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 port g bit 7 654321 bit 0 mcu pin: ptg7 ptg6 ptg5 ptg4 ptg3 ptg2/ extal ptg1/ xtal ptg0/ bkgd/ms
data sheet ?mc9s08gb60/d v1.5 motorola 135 mc9s08gb/gt 8.4 parallel i/o controls provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose i/o pins that are accessed and controlled by a data register (ptxd), a data direction register (ptxdd), a pullup enable register (ptxpe), and a slew rate control register (ptxse) where x is a, b, c, d, e, f, or g. reads of the data register return the pin value (if ptxddn = 0) or the contents of the port data register (if ptxddn = 1). writes to the port data register are latched into the port register whether the pin is controlled by an on-chip peripheral or the pin is configured as an input. if the corresponding pin is not controlled by a peripheral and is configured as an output, this level will be driven out the port pin. 8.4.1 data direction control the data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register reads. each port pin has a data direction control bit. when ptxddn = 0, the corresponding pin is an input and reads of ptxd return the pin value. when ptxddn = 1, the corresponding pin is an output and reads of ptxd return the last value written to the port data register. when a peripheral module or system function is in control of a port pin, the data direction control still controls what is returned for reads of the port data register, even though the peripheral system has overriding control of the actual pin direction. for the mc9s08gb/gt mcu, reads of ptg0/bkgd/ms will return the value on the output pin. it is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. this ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. 8.4.2 internal pullup control an internal pullup device can be enabled for each port pin that is configured as an input (ptxddn = 0). the pullup device is available for a peripheral module to use, provided the peripheral is enabled and is an input function as long as the ptxddn = 0. for the four configurable kbi module inputs on pta7?ta4, when a pin is configured to detect rising edges, the port pullup enable associated with the pin (ptapen) selects a pulldown rather than a pullup device. 8.4.3 slew rate control slew rate control can be enabled for each port pin that is configured as an output (ptxddn = 1) or if a peripheral module is enabled and its function is an output. not all peripheral modules outputs have slew rate control, refer to the pins and connections section for more information about which pins have slew rate control.
parallel input/output mc9s08gb/gt 136 motorola 8.5 stop modes depending on the stop mode, i/o functions differently as the result of executing a stop instruction. an explanation of i/o behavior for the various stop modes follows: stop1 mode is the lowest current stop mode. all i/o states are lost in this mode. upon recovery from stop1, all i/o must be initialized as if the mcu were undergoing an initial power-up. stop2 mode is a partial power-down mode, whereby i/o latches are maintained in their state as before the stop instruction was executed. cpu register status and the state of i/o registers should be saved in ram before the stop instruction is executed to place the mcu in stop2 mode. upon recovery from stop2 mode, before accessing any i/o, the user should examine the state of the ppdf bit in the spmsc2 register. if the ppdf bit is 0, i/o must be initialized as if a power on reset had occurred. if the ppdf bit is 1, i/o data previously stored in ram, before the stop instruction was executed, peripherals may require being initialized and restored to their pre-stop condition. the user must then write a 1 to the ppdack bit in the spmsc2 register. access to i/o is now permitted again in the user? application program. in stop3 mode, all i/o is maintained because internal logic circuity stays powered up. upon recovery, normal i/o function is available to the user. 8.6 parallel i/o registers and control bits this section provides information about all registers and control bits associated with the parallel i/o ports. refer to tables in the memory section for the absolute address assignments for all parallel i/o registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 8.6.1 port a registers (ptad, ptape, ptase, and ptadd) port a includes eight pins shared between general-purpose i/o and the kbi module. port a pins used as general-purpose i/o pins are controlled by the port a data (ptad), data direction (ptadd), pullup enable (ptape) and slew rate control (ptase) registers. if the kbi takes control of a port a pin, the corresponding ptase bit is ignored since the pin functions as an input. as long as ptadd is a logic 0, the ptape controls the pullup enable for the kbi function. reads of ptad will return the logic value of the corresponding pin, provided ptadd is a logic 0.
data sheet ?mc9s08gb60/d v1.5 motorola 137 mc9s08gb/gt figure 8-9 port a registers ptadn port a data register bit n (n = 0?) for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are configured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port a pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. ptapen pullup enable for port a bit n (n = 0?) for port a pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled provided the corresponding ptaddn is a logic 0. for port a pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. when any of bits 7 through 4 of port a are enabled as kbi inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. 1 = internal pullup device enabled. 0 = internal pullup device disabled. ptad bit 7 654321 bit 0 read: ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 write: reset: 00000000 ptape read: ptape7 ptape6 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 write: reset: 00000000 ptase read: ptase7 ptase6 ptase5 ptase4 ptase3 ptase2 ptase1 ptase0 write: reset: 00000000 ptadd read: ptadd7 ptadd6 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 write: reset: 00000000
parallel input/output mc9s08gb/gt 138 motorola ptasen slew rate control enable for port a bit n (n = 0?) for port a pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. for port a pins that are configured as inputs, these bits are ignored. 1 = slew rate control enabled. 0 = slew rate control disabled. ptaddn data direction for port a bit n (n = 0?) these read/write bits control the direction of port a pins and what is read for ptad reads. 1 = output driver enabled for port a bit n and ptad reads return the contents of ptadn. 0 = input (output driver disabled) and reads return the pin value. 8.6.2 port b registers (ptbd, ptbpe, ptbse, and ptbdd) port b includes eight general-purpose i/o pins that share with the atd function. port b pins used as general-purpose i/o pins are controlled by the port b data (ptbd), data direction (ptbdd), pullup enable (ptbpe) and slew rate control (ptbse) registers. if the atd takes control of a port b pin, the corresponding ptbdd, ptbse, ptbpe bits are ignored. when a port b pin is being used as an atd pin, reads of ptbd will return a logic 0 of the corresponding pin, provided ptbdd is a logic 0. figure 8-10 port b registers ptbd bit 7 654321 bit 0 read: ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 write: reset: 00000000 ptbpe read: ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 write: reset: 00000000 ptbse read: ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 write: reset: 00000000 ptbdd read: ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 139 mc9s08gb/gt ptbdn port b data register bit n (n = 0?) for port b pins that are inputs, reads return the logic level on the pin. for port b pins that are configured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port b pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptbd to all 0s, but these 0s are not driven out on the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. ptbpen pullup enable for port b bit n (n = 0?) for port b pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port b pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 1 = internal pullup device enabled. 0 = internal pullup device disabled. ptbsen slew rate control enable for port b bit n (n = 0?) for port b pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. for port b pins that are configured as inputs, these bits are ignored. 1 = slew rate control enabled. 0 = slew rate control disabled. ptbddn data direction for port b bit n (n = 0?) these read/write bits control the direction of port b pins and what is read for ptbd reads. 1 = output driver enabled for port b bit n and ptbd reads return the contents of ptbdn. 0 = input (output driver disabled) and reads return the pin value. 8.6.3 port c registers (ptcd, ptcpe, ptcse, and ptcdd) port c includes eight general-purpose i/o pins that share with the sci2 and iic modules. port c pins used as general-purpose i/o pins are controlled by the port c data (ptcd), data direction (ptcdd), pullup enable (ptcpe) and slew rate control (ptcse) registers. if the sci2 takes control of a port c pin, the corresponding ptcdd bit are ignored. ptcse can be used to provide slew rate on the sci2 transmit pin, txd2. ptcpe can be used, provided the corresponding ptcdd bit is a logic 0, to provide a pullup device on the sci2 receive pin, rxd2. if the iic takes control of a port c pin, the corresponding ptcdd bit are ignored. ptcse can be used to provide slew rate on the iic serial data pin (sda), when in output mode and the iic clock pin (scl). ptcpe can be used, provided the corresponding ptcdd bit is a logic 0, to provide a pullup device on the iic serial data pin, when in receive mode. reads of ptcd will return the logic value of the corresponding pin, provided ptcdd is a logic 0.
parallel input/output mc9s08gb/gt 140 motorola figure 8-11 port c registers ptcdn port c data register bit n (n = 0?) for port c pins that are inputs, reads return the logic level on the pin. for port c pins that are configured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port c pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptcd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. ptcpen pullup enable for port c bit n (n = 0?) for port c pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port c pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 1 = internal pullup device enabled. 0 = internal pullup device disabled. ptcsen slew rate control enable for port c bit n (n = 0?) for port c pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. for port b pins that are configured as inputs, these bits are ignored. 1 = slew rate control enabled. 0 = slew rate control disabled. ptcd bit 7 654321 bit 0 read: ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 write: reset: 00000000 ptcpe read: ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 write: reset: 00000000 ptcse read: ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 write: reset: 00000000 ptcdd read: ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 141 mc9s08gb/gt ptcddn data direction for port c bit n (n = 0?) these read/write bits control the direction of port c pins and what is read for ptcd reads. 1 = output driver enabled for port c bit n and ptcd reads return the contents of ptcdn. 0 = input (output driver disabled) and reads return the pin value. 8.6.4 port d registers (ptdd, ptdpe, ptdse, and ptddd) port d includes eight pins shared between general-purpose i/o, tpm1 and tpm2. port d pins used as general-purpose i/o pins are controlled by the port d data (ptdd), data direction (ptddd) and pullup enable (ptdpe) and slew rate control (ptdse) registers. if a tpm takes control of a port d pin, the corresponding ptddd bit are ignored. when the tpm is in output compare mode, the corresponding ptdse can be used to provide slew rate on the pin. when the tpm is in input capture mode, the corresponding ptdpe can be used, provided the corresponding ptddd bit is a logic 0, to provide a pullup device on the pin. reads of ptdd will return the logic value of the corresponding pin, provided ptddd is a logic 0. figure 8-12 port d registers ptdd bit 7 654321 bit 0 read: ptdd7 ptdd6 ptdd5 ptdd4 ptdd3 ptdd2 ptdd1 ptdd0 write: reset: 00000000 ptdpe read: ptdpe7 ptdpe6 ptdpe5 ptdpe4 ptdpe3 ptdpe2 ptdpe1 ptdpe0 write: reset: 00000000 ptdse read: ptdse7 ptdse6 ptdse5 ptdse4 ptdse3 ptdse2 ptdse1 ptdse0 write: reset: 00000000 ptddd read: ptddd7 ptddd6 ptddd5 ptddd4 ptddd3 ptddd2 ptddd1 ptddd0 write: reset: 00000000
parallel input/output mc9s08gb/gt 142 motorola ptddn port d data register bit n (n = 0?) for port d pins that are inputs, reads return the logic level on the pin. for port d pins that are configured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port d pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptdd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. ptdpen pullup enable for port d bit n (n = 0?) for port d pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port d pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 1 = internal pullup device enabled. 0 = internal pullup device disabled. ptdsen slew rate control enable for port d bit n (n = 0?) for port d pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. for port d pins that are configured as inputs, these bits are ignored. 1 = slew rate control enabled. 0 = slew rate control disabled. ptdddn data direction for port d bit n (n = 0?) these read/write bits control the direction of port d pins and what is read for ptdd reads. 1 = output driver enabled for port d bit n and ptdd reads return the contents of ptddn. 0 = input (output driver disabled) and reads return the pin value. 8.6.5 port e registers (pted, ptepe, ptese, and ptedd) port e includes eight general-purpose i/o pins that share with the sci1 and spi modules. port e pins used as general-purpose i/o pins are controlled by the port e data (pted), data direction (ptedd), pullup enable (ptepe) and slew rate control (ptese) registers. if the sci1 takes control of a port e pin, the corresponding ptedd bit are ignored. ptese can be used to provide slew rate on the sci1 transmit pin, txd1. ptepe can be used, provided the corresponding ptedd bit is a logic 0, to provide a pullup device on the sci1 receive pin, rxd1. if the spi takes control of a port e pin, the corresponding ptedd bit are ignored. ptese can be used to provide slew rate on the spi serial output pin (mosi or miso) and serial clock pin (spclk) depending on the spi operational mode. ptepe can be used, provided the corresponding ptedd bit is a logic 0, to provide a pullup device on the spi serial input pins (mosi or miso) and slave select pin ( ss) depending on the spi operational mode. reads of pted will return the logic value of the corresponding pin, provided ptedd is a logic 0.
data sheet ?mc9s08gb60/d v1.5 motorola 143 mc9s08gb/gt figure 8-13 port e registers ptedn port e data register bit n (n = 0?) for port e pins that are inputs, reads return the logic level on the pin. for port e pins that are configured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port e pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces pted to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. ptepen pullup enable for port e bit n (n = 0?) for port e pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port e pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 1 = internal pullup device enabled. 0 = internal pullup device disabled. ptesen slew rate control enable for port e bit n (n = 0?) for port e pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. for port e pins that are configured as inputs, these bits are ignored. 1 = slew rate control enabled. 0 = slew rate control disabled. pted bit 7 654321 bit 0 read: pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 write: reset: 00000000 ptepe read: ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 write: reset: 00000000 ptese read: ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 write: reset: 00000000 ptedd read: ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 write: reset: 00000000
parallel input/output mc9s08gb/gt 144 motorola pteddn data direction for port e bit n (n = 0?) these read/write bits control the direction of port e pins and what is read for pted reads. 1 = output driver enabled for port e bit n and pted reads return the contents of ptedn. 0 = input (output driver disabled) and reads return the pin value. 8.6.6 port f registers (ptfd, ptfpe, ptfse, and ptfdd) port f includes eight general-purpose i/o pins that are not shared with any peripheral module. port f pins used as general-purpose i/o pins are controlled by the port f data (ptfd), data direction (ptfdd), pullup enable (ptfpe), and slew rate control (ptfse) registers. figure 8-14 port f registers ptfdn port ptf data register bit n (n = 0?) for port f pins that are inputs, reads return the logic level on the pin. for port f pins that are configured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port f pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptfd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. ptfd bit 7 654321 bit 0 read: ptfd7 ptfd6 ptfd5 ptfd4 ptfd3 ptfd2 ptfd1 ptfd0 write: reset: 00000000 ptfpe read: ptfpe7 ptfpe6 ptfpe5 ptfpe4 ptfpe3 ptfpe2 ptfpe1 ptfpe0 write: reset: 00000000 ptfse read: ptfse7 ptfse6 ptfse5 ptfse4 ptfse3 ptfse2 ptfse1 ptfse0 write: reset: 00000000 ptfdd read: ptfdd7 ptfdd6 ptfdd5 ptfdd4 ptfdd3 ptfdd2 ptfdd1 ptfdd0 write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 145 mc9s08gb/gt ptfpen pullup enable for port f bit n (n = 0?) for port f pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port f pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 1 = internal pullup device enabled. 0 = internal pullup device disabled. ptfsen slew rate control enable for port f bit n (n = 0?) for port f pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. for port f pins that are configured as inputs, these bits are ignored. 1 = slew rate control enabled. 0 = slew rate control disabled. ptfddn data direction for port f bit n (n = 0?) these read/write bits control the direction of port f pins and what is read for ptfd reads. 1 = output driver enabled for port f bit n and ptfd reads return the contents of ptfdn. 0 = input (output driver disabled) and reads return the pin value. 8.6.7 port g registers (ptgd, ptgpe, ptgse, and ptgdd) port g includes eight general-purpose i/o pins that are shared with bkgd/ms function and the oscillator or external clock pins. port g pins used as general-purpose i/o pins are controlled by the port g data (ptgd), data direction (ptgdd), pullup enable (ptgpe), and slew rate control (ptgse) registers. port pin ptg0, while in reset, defaults to the bkgd/ms pin. once the mcu is out of reset, ptg0 can be configured to be a general-purpose output pin. when bkgd/ms takes control of ptg0, the corresponding ptgdd, ptgpe, and ptgpse bits are ignored. port pin ptg1 and ptg2 can be configured to be oscillator or external clock pins. when the oscillator takes control of a port g pin, the corresponding ptgd, ptgdd, ptgse, and ptgpe bits are ignored. reads of ptgd will return the logic value of the corresponding pin, provided ptgdd is a logic 0.
parallel input/output mc9s08gb/gt 146 motorola figure 8-15 port g registers ptgdn port ptg data register bit n (n = 0?) for port g pins that are inputs, reads return the logic level on the pin. for port g pins that are configured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port g pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptgd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. ptgpen pullup enable for port g bit n (n = 0?) for port g pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. for port g pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 1 = internal pullup device enabled. 0 = internal pullup device disabled. ptgsen slew rate control enable for port g bit n (n = 0?) for port g pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. for port g pins that are configured as inputs, these bits are ignored. 1 = slew rate control enabled. 0 = slew rate control disabled. ptgd bit 7 654321 bit 0 read: ptgd7 ptgd6 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 write: reset: 00000000 ptgpe read: ptgpe7 ptgpe6 ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 write: reset: 00000000 ptgse read: ptgse7 ptgse6 ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 write: reset: 00000000 ptgdd read: ptgdd7 ptgdd6 ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 147 mc9s08gb/gt ptgddn data direction for port g bit n (n = 0?) these read/write bits control the direction of port g pins and what is read for ptgd reads. 1 = output driver enabled for port g bit n and ptgd reads return the contents of ptgdn. 0 = input (output driver disabled) and reads return the pin value.
parallel input/output mc9s08gb/gt 148 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 149 mc9s08gb/gt section 9 keyboard interrupt (kbi) module 9.1 introduction the mc9s08gb/gt has one kbi module with eight keyboard interrupt inputs that share port a pins. see the pins and connections section for more information about the logic and hardware aspects of these pins. 9.1.1 port a and keyboard interrupt pins figure 9-1 port a pin names the following paragraphs discuss controlling the keyboard interrupt pins. port a is an 8-bit port which is shared among the kbi keyboard interrupt inputs and general-purpose i/o. the eight kbipen control bits in the kbipe register allow selection of any combination of port a pins to be assigned as kbi inputs. any pins which are enabled as kbi inputs will be forced to act as inputs and the remaining port a pins are available as general-purpose i/o pins controlled by the port a data (ptad), data direction (ptadd) and pullup enable (ptape) registers. kbi inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. bits 3 through 0 of port a are falling-edge/low-level sensitive while bits 7 through 4 can be configured for rising-edge/high-level or for falling-edge/low-level sensitivity. the eight ptapen control bits in the ptape register allow you to select whether an internal pullup device is enabled on each port a pin that is configured as an input. when any of bits 7 through 4 of port a are enabled as kbi inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. an enabled keyboard interrupt can be used to wake the mcu from wait or standby (stop3). 9.2 features the keyboard interrupt (kbi) module features include: keyboard interrupts selectable on eight port pins: four falling edge/low level sensitive four falling edge/low level or rising edge/high level sensitive choice of edge-only or edge-and-level sensitivity common interrupt flag and interrupt enable control capable of waking up the mcu from stop3 or wait mode mcu pin: pta7/ kbip7 pta6/ kbip6 pta5/ kbip5 pta4/ kbip4 pta3/ kbip3 pta2/ kbip2 pta1/ kbip1 pta0/ kbip0
keyboard interrupt (kbi) module mc9s08gb/gt 150 motorola figure 9-2 block diagram highlighting kbi module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5
data sheet ?mc9s08gb60/d v1.5 motorola 151 mc9s08gb/gt 9.3 kbi block diagram figure 9-3 shows the block diagram for a kbi module. figure 9-3 kbi block diagram the kbi module allows up to eight pins to act as additional interrupt sources. four of these pins allow falling-edge sensing while the other four can be configured for either rising-edge sensing or falling-edge sensing. the sensing mode for all eight pins can also be modified to detect edges and levels instead of just edges. 9.4 keyboard interrupt (kbi) module this on-chip peripheral module is called a keyboard interrupt (kbi) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. however, these inputs are also useful as extra external interrupt inputs and as an external means of waking up the mcu from stop or wait low-power modes. 9.4.1 pin enables the kbipen control bits in the kbipe register allow a user to enable (kbipen = 1) any combination of kbi-related port pins to be connected to the kbi module. pins corresponding to 0s in kbipe are general-purpose i/o pins that are not associated with the kbi module. 9.4.2 edge and level sensitivity synchronous logic is used to detect edges. prior to detecting an edge, enabled keyboard inputs in a kbi module must be at the deasserted logic level. keyboard interrupt dq ck clr v dd kbimod kbie keyboard interrupt ff request kback reset synchronizer kbf stop bypass stop busclk kbipen 0 1 s kbedgn kbipe0 kbipe3 kbipe4 0 1 s kbedg4 kbip0 kbip3 kbip4 kbipn
keyboard interrupt (kbi) module mc9s08gb/gt 152 motorola a falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. the kbimod control bit can be set to reconfigure the detection logic so that it detects edges and levels. in kbimod = 1 mode, the kbf status flag becomes set when an edge is detected (when one or more enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their deasserted levels), but the flag is continuously set (and cannot be cleared) as long as any enabled keyboard input pin remains at the asserted level. when the mcu enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). in stop mode, kbi inputs act as asynchronous level-sensitive inputs so they can wake the mcu from stop mode. 9.4.3 kbi interrupt controls the kbf status flag becomes set (1) when an edge event has been detected on any kbi input pin. if kbie = 1 in the kbisc register, a hardware interrupt will be requested whenever kbf = 1. the kbf flag is cleared by writing a 1 to the keyboard acknowledge (kback) bit. when kbimod = 0 (selecting edge-only operation), kbf is always cleared by writing 1 to kback. when kbimod = 1 (selecting edge-and-level operation), kbf cannot be cleared as long as any keyboard input is at its asserted level. 9.5 kbi registers and control bits this section provides information about all registers and control bits associated with the kbi modules. refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all kbi registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. 9.5.1 kbi status and control register (kbisc) figure 9-4 kbi status and control register (kbisc) bit 7 654321 bit 0 read: kbedg7 kbedg6 kbedg5 kbedg4 kbf 0 kbie kbimod write: kback reset: 00000000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 153 mc9s08gb/gt kbedgn keyboard edge select for kbi port bit n (n = 7?) each of these read/write bits selects the polarity of the edges and/or levels that are recognized as trigger events on the corresponding kbi port pin when it is configured as a keyboard interrupt input (kbipen = 1). also see the kbimod control bit which determines whether the pin is sensitive to edges-only or edges and levels. 1 = rising edges/high levels. 0 = falling edges/low levels. kbf keyboard interrupt flag this read-only status flag is set whenever the selected edge event has been detected on any of the enabled kbi port pins. this flag is cleared by writing a logic 1 to the kback control bit. the flag will remain set if kbimod = 1 to select edge-and-level operation and any enabled kbi port pin remains at the asserted level. 1 = kbi interrupt pending. 0 = no kbi interrupt pending. kbf can be used as a software pollable flag (kbie = 0) or it can generate a hardware interrupt request to the cpu (kbie = 1). kback keyboard interrupt acknowledge this write-only bit (reads always return 0) is used to clear the kbf status flag by writing a logic 1 to kback. when kbimod = 1 to select edge-and-level operation and any enabled kbi port pin remains at the asserted level, kbf is being continuously set so writing 1 to kback does not clear the kbf flag. kbie keyboard interrupt enable this read/write control bit determines whether hardware interrupts are generated when the kbf status flag equals 1. when kbie = 0, no hardware interrupts are generated, but kbf can still be used for software polling. 1 = kbi hardware interrupt requested when kbf = 1. 0 = kbf does not generate hardware interrupts (use polling). kbimod keyboard detection mode this read/write control bit selects either edge-only detection or edge-and-level detection. kbi port bits 3 through 0 can detect falling edges-only or falling edges and low levels. kbi port bits 7 through 4 can be configured to detect either: rising edges-only or rising edges and high levels (kbedgn = 1) falling edges-only or falling edges and low levels (kbedgn = 0) 1 = edge-and-level detection. 0 = edge-only detection.
keyboard interrupt (kbi) module mc9s08gb/gt 154 motorola 9.5.2 kbi pin enable register (kbipe) figure 9-5 kbi pin enable register (kbipe) kbipen keyboard pin enable for kbi port bit n (n = 7?) each of these read/write bits selects whether the associated kbi port pin is enabled as a keyboard interrupt input or functions as a general-purpose i/o pin. 1 = bit n of kbi port enabled as a keyboard interrupt input 0 = bit n of kbi port is a general-purpose i/o pin not associated with the kbi. bit 7 654321 bit 0 read: kbipe7 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 155 mc9s08gb/gt section 10 timer/pwm (tpm) module 10.1 introduction the mc9s08gb/gt includes two independent timer/pwm (tpm) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (pwm) on each channel. a control bit in each tpm configures all channels in that timer to operate as center-aligned pwm functions. in each of these two tpms, timing functions are based on a separate 16-bit counter with prescaler and modulo features to control frequency and range (period between overflows) of the time reference. this timing system is ideally suited for a wide range of control applications, and the center-aligned pwm capability on the 3-channel tpm extends the field of applications to motor control in small appliances. the fixed system clock xclk is normally the oscillator rate divided by two (icgerclk/2). if the pll or fll is engaged and locked, and the bus rate (busclk) is not at least two times the icgerclk frequency, xclk equals busclk instead of icgerclk/2. 10.2 features the timer system in the mc9s08gbxx includes a 3-channel tpm1 and a separate 5-channel tpm2; the timer system in the mc9s08gtxx includes two 2-channel modules, tpm1 and tpm2. timer system features include: a total of eight channels: each channel may be input capture, output compare, or buffered edge-aligned pwm rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action selectable polarity on pwm outputs each tpm may be configured for buffered, center-aligned pulse-width modulation (cpwm) on all channels clock source to prescaler for each tpm is independently selectable as bus clock, fixed system clock, or an external pin: prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 fixed system clock (xclk) and pin paths are synchronized external clocks shared with tpmxch0 timer channel pins 16-bit free-running or up/down (cpwm) count operation 16-bit modulus register to control counter range timer system enable one interrupt per channel plus terminal count interrupt
timer/pwm (tpm) module mc9s08gb/gt 156 motorola figure 10-1 block diagram highlighting the tpm module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5
data sheet ?mc9s08gb60/d v1.5 motorola 157 mc9s08gb/gt 10.3 tpm block diagram the tpm uses one input/output (i/o) pin per channel, tpmxchn where x is the tpm number (for example, 1 or 2) and n is the channel number (for example, 0?). the tpm shares its i/o pins with general-purpose i/o port pins (refer to the pins and connections section for more information). figure 10-2 shows the structure of a tpm. some mcus include more than one tpm, with various numbers of channels. figure 10-2 tpm block diagram prescale and select 16-bit comparator main 16-bit counter 16-bit comparator 16-bit latch port 16-bit comparator 16-bit latch channel 0 channel 1 internal bus logic interrupt port logic 16-bit comparator 16-bit latch channel n port logic counter reset divide by clock source off, bus, xclk, ext busclk xclk select sync interrupt interrupt interrupt 1, 2, 4, 8, 16, 32, 64, or 128 logic logic logic logic clksa clksb ps2 ps1 ps0 cpwms toie tof els0a ch0f els0b els1b els1a elsnb elsna ch1f chnf ch0ie ch1ie chnie ms1b ms0b msnb ms0a ms1a msna . . . . . . . . . tpmxmodh:tpmxmodl tpmx) ext clk tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxcnvh:tpmxcnvl tpmxchn tpmxch1 tpmxch0
timer/pwm (tpm) module mc9s08gb/gt 158 motorola the central component of the tpm is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up/down counter when the tpm is configured for center-aligned pwm. the tpm counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned pwm functions. the timer counter modulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter. (the values $0000 or $ffff effectively make the counter free running.) software can read the counter value at any time without affecting the counting sequence. any write to either byte of the tpmxcnt counter resets the counter regardless of the data value written. all tpm channels are programmable independently as input capture, output compare, or buffered edge-aligned pwm channels. 10.4 pin descriptions table 10-1 shows the mcu pins related to the tpm modules. when tpmxch0 is used as an external clock input, the associated tpm channel 0 may not use the pin. (channel 0 could still be used in output compare mode as a software timer.) when any of the pins associated with the timer is acting as a general-purpose input or as a timer input, a passive pullup can be enabled. after reset, the tpm modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 10.4.1 external tpm clock sources when control bits clksb:clksa in the timer status and control register are set to 1:1, the prescaler and subsequently the 16-bit counter for tpmx are driven by an external clock source connected to the tpmxch0 pin. a synchronizer is needed between the external clock and the rest of the tpm. this synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency of the bus rate clock. the upper frequency limit for this external clock source is specified to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (pll) or frequency-locked loop (fll) frequency jitter effects. when the tpm is using the channel 0 pin for an external clock, the corresponding els0b:els0a control bits should be set to 0:0 so channel 0 is not trying to use the same pin. 10.4.2 tpmxchn ?tpmx channel n i/o pins each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the configuration of the channel. in some cases no pin function is needed so the pin reverts to being controlled by general-purpose i/o controls. when a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). see the pins and connections section for additional information about shared pin functions.
data sheet ?mc9s08gb60/d v1.5 motorola 159 mc9s08gb/gt 10.5 functional description all tpm functions are associated with a main 16-bit counter which allows flexible selection of the clock source and prescale divisor. a 16-bit modulo register also is associated with the main 16-bit counter in the tpm. each tpm channel is optionally associated with an mcu pin and a maskable interrupt function. the tpm has center-aligned pwm capabilities controlled by the cpwms control bit in tpmxsc. when cpwms is set to 1, timer counter tpmxcnt changes to an up/down counter and all channels in the associated tpm act as center-aligned pwm channels. when cpwms = 0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-aligned pwm mode. the following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 10.5.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, up-counting vs. up/down-counting, end-of-count overflow, and manual counter reset. after any mcu reset, clksb:clksa = 0:0 so no clock source is selected and the tpm is inactive. normally, clksb:clksa would be set to 0:1 so the bus clock drives the timer counter. the clock source for each of the tpm can be independently selected to be off, the bus clock (busclk), the fixed system clock (xclk), or an external input through the tpmxch0 pin. the maximum frequency allowed for the external clock option is one-fourth the bus rate. refer to 10.7.1 timer x status and control register (tpmxsc) and table 10-1 for more information about clock source selection. when the microcontroller is in active background mode, the tpm temporarily suspends all counting until the microcontroller returns to normal user operating mode. during stop mode, all tpm clocks are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to operate normally. the main 16-bit counter has two counting modes. when center-aligned pwm is selected (cpwms = 1), the counter operates in up/down-counting mode. otherwise, the counter operates as a simple up counter. as an up counter, the main 16-bit counter counts from $0000 through its terminal count and then continues with $0000. the terminal count is $ffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is specified, the counter counts upward from $0000 through its terminal count and then counts downward to $0000 where it returns to up-counting. both $0000 and the terminal count value (value in tpmxmodh:tpmxmodl) are normal length counts (one timer clock period long). an interrupt flag and enable are associated with the main 16-bit counter. the timer overflow flag (tof) is a software-accessible indication that the timer counter has overflowed. the enable signal selects between software polling (toie = 0) where no hardware interrupt is generated, or interrupt-driven
timer/pwm (tpm) module mc9s08gb/gt 160 motorola operation (toie = 1) where a static hardware interrupt is automatically generated whenever the tof flag is equal to one. the conditions which cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the main 16-bit counter counts from $0000 through $ffff and overflows to $0000 on the next counting clock. tof becomes set at the transition from $ffff to $0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to $0000. when the main 16-bit counter is operating in up/down-counting mode, the tof flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. this corresponds to the end of a pwm period. (the $0000 count value corresponds to the center of a period.) because the hcs08 is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. whenever either byte of the counter is read (tpmxcnth or tpmxcntl), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the first byte was read. the counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. the main timer counter can be reset manually at any time by writing any value to either byte of the timer count tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. 10.5.2 channel mode selection provided cpwms = 0 (center-aligned pwm operation is not specified), the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and buffered edge-aligned pwm. 10.5.2.1 input capture mode with the input capture function, the tpm can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tpm latches the contents of the tpm counter into the channel value registers (tpmxcnvh:tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. when either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. the coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an input capture event sets a flag bit (chnf) which can optionally generate a cpu interrupt request. 10.5.2.2 output compare mode with the output compare function, the tpm can generate timed pulses with programmable position, polarity, duration, and frequency. when the counter reaches the value in the channel value registers of an output compare channel, the tpm can set, clear, or toggle the channel pin. in output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. this coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc).
data sheet ?mc9s08gb60/d v1.5 motorola 161 mc9s08gb/gt an output compare event sets a flag bit (chnf) which can optionally generate a cpu interrupt request. 10.5.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counting mode of the timer counter (cpwms = 0) and can be used when other channels in the same tpm are configured for input capture or output compare functions. the period of this pwm signal is determined by the setting in the modulus register (tpmxmodh:tpmxmodl). the duty cycle is determined by the setting in the timer channel value register (tpmxcnvh:tpmxcnvl). the polarity of this pwm signal is determined by the setting in the elsna control bit. duty cycle cases of 0 percent and 100 percent are possible. as figure 10-3 shows, the output compare value in the tpm channel registers determines the pulse width (duty cycle) of the pwm signal. the time between the modulus overflow and the output compare is the pulse width. if elsna = 0, the counter overflow forces the pwm signal high and the output compare forces the pwm signal low. if elsna = 1, the counter overflow forces the pwm signal low and the output compare forces the pwm signal high. figure 10-3 pwm period and pulse width (elsna = 0) when the channel value register is set to $0000, the duty cycle is 0 percent. by setting the timer channel value register (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting, 100 percent duty cycle can be achieved. this implies that the modulus setting must be less than $ffff to get 100 percent duty cycle. because the hcs08 is a family of 8-bit mcus, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to either register, tpmxcnvh or tpmxcnvl, write to buffer registers. in edge-pwm mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the tpmxcnth:tpmxcntl counter is $0000. (the new duty cycle does not take effect until the next full period.) 10.5.3 center-aligned pwm mode this type of pwm output uses the up/down-counting mode of the timer counter (cpwms = 1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal and the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of $0001 to $7fff because values outside this range can produce ambiguous results. elsna will determine the polarity of the cpwm output. period pulse width overflow overflow overflow output compare output compare output compare tpmxchn
timer/pwm (tpm) module mc9s08gb/gt 162 motorola equation 1 pulse width = 2 x (tpmxcnvh:tpmxcnvl) equation 2 period = 2 x (tpmxmodh:tpmxmodl); for tpmxmodh:tpmxmodl = $0001?7fff if the channel value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0 percent. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is $0001 through $7ffe ($7fff if generation of 100 percent duty cycle is not necessary). this is not a significant limitation because the resulting period is much longer than required for normal applications. tpmxmodh:tpmxmodl = $0000 is a special case that should not be used with center-aligned pwm mode. when cpwms = 0, this case corresponds to the counter running free from $0000 through $ffff, but when cpwms = 1 the counter needs a valid match to the modulus register somewhere other than at $0000 in order to change directions from up-counting to down-counting. figure 10-4 shows the output compare value in the tpm channel registers (multiplied by 2) determines the pulse width (duty cycle) of the cpwm signal. if elsna = 0, the compare match while counting up forces the cpwm output signal low and a compare match while counting down forces the output high. the counter counts up until it reaches the modulo setting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to two times tpmxmodh:tpmxmodl. figure 10-4 cpwm period and pulse width (elsna = 0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also required for some types of motor drives. because the hcs08 is a family of 8-bit mcus, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers, tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl, actually write to buffer registers. values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). this tpmxcnt overflow requirement only applies to pwm channels, not output compares. period pulse width count = count = 0 output compare (count up) output compare (count down) count = tpmxmodh:tpmxmodl tpmxchn tpmxmodh:tpmxmodl 2 x tpmxcnvh:tpmxcnvl 2 x tpmxmodh:tpmxmodl
data sheet ?mc9s08gb60/d v1.5 motorola 163 mc9s08gb/gt optionally, when tpmxcnth:tpmxcntl = tpmxmodh:tpmxmodl, the tpm can generate a tof interrupt at the end of this count. the user can choose to reload any number of the pwm buffers, and they will all update simultaneously at the start of a new period. writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo registers. writing to tpmxcnsc cancels any values written to the channel value registers and resets the coherency mechanism for tpmxcnvh:tpmxcnvl. 10.6 tpm interrupts the tpm generates an optional interrupt for the main counter overflow and an interrupt for each channel. the meaning of channel interrupts depends on the mode of operation for each channel. if the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized. if the channel is configured for output compare or pwm modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. see the resets, interrupts, and system configuration section for absolute interrupt vector addresses, priority, and local interrupt mask control bits. for each interrupt source in the tpm, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel input capture, or output compare events. this flag may be read (polled) by software to determine that the action has occurred, or an associated enable bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. it is the responsibility of user software to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine. 10.6.1 clearing timer interrupt flags tpm interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1) followed by a write of zero (0) to the bit. if a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 10.6.2 timer overflow interrupt description the conditions which cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the 16-bit timer counter counts from $0000 through $ffff and overflows to $0000 on the next counting clock. tof becomes set at the transition from $ffff to $0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to $0000. when the counter is operating in up/down-counting mode, the tof flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. this corresponds to the end of a pwm period. (the $0000 count value corresponds to the center of a period.) 10.6.3 channel event interrupt description the meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned pwm, or center-aligned pwm).
timer/pwm (tpm) module mc9s08gb/gt 164 motorola when a channel is configured as an input capture channel, the elsnb:elsna control bits select rising edges, falling edges, any edge, or no edge (off) as the edge which triggers an input capture event. when the selected edge is detected, the interrupt flag is set. the flag is cleared by the 2-step sequence described in 10.6.1 clearing timer interrupt flags . when a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. the flag is cleared by the 2-step sequence described in 10.6.1 clearing timer interrupt flags . 10.6.4 pwm end-of-duty-cycle events for channels that are configured for pwm operation, there are two possibilities: when the channel is configured for edge-aligned pwm, the channel flag is set when the timer counter matches the channel value register which marks the end of the active duty cycle period. when the channel is configured for center-aligned pwm, the timer count matches the channel value register twice during each pwm cycle. in this cpwm case, the channel flag is set at the start and at the end of the active duty cycle which are the times when the timer counter matches the channel value register. the flag is cleared by the 2-step sequence described in 10.6.1 clearing timer interrupt flags . 10.7 tpm registers and control bits the tpm includes: an 8-bit status and control register (tpmxsc) a 16-bit counter (tpmxcnth:tpmxcntl) a 16-bit modulo register (tpmxmodh:tpmxmodl) each timer channel has: an 8-bit status and control register (tpmxcnsc) a 16-bit channel value register (tpmxcnvh:tpmxcnvl) refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all tpm registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. some mcu systems have more than one tpm, so register names include placeholder characters to identify which tpm and which channel is being referenced. for example, tpmxcnsc refers to timer (tpm) x, channel n and tpm1c2sc is the status and control register for timer 1, channel 2.
data sheet ?mc9s08gb60/d v1.5 motorola 165 mc9s08gb/gt 10.7.1 timer x status and control register (tpmxsc) tpmxsc contains the overflow status flag and control bits which are used to configure the interrupt enable, tpm configuration, clock source, and prescale divisor. these controls relate to all channels within this timer module. figure 10-5 timer x status and control register (tpmxsc) tof timer overflow flag this flag is set when the tpm counter changes to $0000 after reaching the modulo value programmed in the tpm counter modulo registers. when the tpm is configured for cpwm, tof is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. clear tof by reading the tpm status and control register when tof is set and then writing a logic 0 to tof. if another tpm overflow occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tpm counter has overflowed. 0 = tpm counter has not reached modulo value or overflow. toie timer overflow interrupt enable this read/write bit enables tpm overflow interrupts. if toie is set, an interrupt is generated when tof equals 1. reset clears toie. 1 = tof interrupts enabled. 0 = tof interrupts inhibited (use software polling). cpwms center-aligned pwm select this read/write bit selects cpwm operating mode. reset clears this bit so the tpm operates in up-counting mode for input capture, output compare, and edge-aligned pwm functions. setting cpwms reconfigures the tpm to operate in up/down-counting mode for cpwm functions. reset clears the cpwms bit. 1 = all tpmx channels operate in center-aligned pwm mode. 0 = all tpmx channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each channel? status and control register. bit 7 654321 bit 0 read: tof toie cpwms clksb clksa ps2 ps1 ps0 write: reset: 00000000 = unimplemented or reserved
timer/pwm (tpm) module mc9s08gb/gt 166 motorola clksb:clksa clock source select as shown in table 10-1 , this 2-bit field is used to disable the tpm system or select one of three clock sources to drive the counter prescaler. the external source and the crystal source are synchronized to the bus clock by an on-chip synchronization circuit. ps2:ps1:ps0 prescale divisor select this 3-bit field selects one of eight divisors for the tpm clock input as shown in table 10-2 . this prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the tpm system. 10.7.2 timer x counter registers (tpmxcnth:tpmxcntl) the two read-only tpm counter registers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. this allows coherent 16-bit reads in either order. the table 10-1 tpm clock source selection clksb:clksa tpm clock source to prescaler input 0:0 no clock selected (tpm disabled) 0:1 bus rate clock (busclk) 1:0 fixed system clock (xclk) 1:1 external source (tpmx ext clk) (1)(2) notes : 1. the maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2. when the tpmxch0 pin is selected as the tpm clock source, the corresponding els0b:els0a control bits should be set to 0:0 so channel 0 does not try to use the same pin for a conflicting function. table 10-2 prescale divisor selection ps2:ps1:ps0 tpm clock source divided-by 0:0:0 1 0:0:1 2 0:1:0 4 0:1:1 8 1:0:0 16 1:0:1 32 1:1:0 64 1:1:1 128
data sheet ?mc9s08gb60/d v1.5 motorola 167 mc9s08gb/gt coherency mechanism is automatically restarted by an mcu reset, a write of any value to tpmxcnth or tpmxcntl, or any write to the timer status/control register (tpmxsc). reset clears the tpm counter registers. figure 10-6 timer x counter register high (tpmxcnth) figure 10-7 timer x counter register low (tpmxcntl) when background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 10.7.3 timer x counter modulo registers (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from $0000 at the next clock (cpwms = 0) or starts counting down (cpwms = 1), and the overflow flag (tof) becomes set. writing to tpmxmodh or tpmxmodl inhibits the tof bit and overflow interrupts until the other byte is written. reset sets the tpm counter modulo registers to $0000 which results in a free-running timer counter (modulo disabled). figure 10-8 timer x counter modulo register high (tpmxmodh) bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: any write to tpmxcnth clears the 16-bit counter. reset: 00000000 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: any write to tpmxcntl clears the 16-bit counter. reset: 00000000 bit 7 654332 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000
timer/pwm (tpm) module mc9s08gb/gt 168 motorola figure 10-9 timer x counter modulo register low (tpmxmodl) it is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow. an alternative approach is to reset the tpm counter before writing to the tpm modulo registers to avoid confusion about when the first counter overflow will occur. 10.7.4 timer x channel n status and control register (tpmxcnsc) tpmxcnsc contains the channel interrupt status flag and control bits which are used to configure the interrupt enable, channel configuration, and pin function. figure 10-10 timer x channel n status and control register (tpmxcnsc) chnf channel n flag when channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel n pin. when channel n is an output compare or edge-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. this flag is seldom used with center-aligned pwms because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a logic 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf would remain set after the clear sequence was completed for the earlier chnf. this is done so a chnf interrupt request cannot be lost by clearing a previous chnf. reset clears the chnf bit. writing a logic 1 to chnf has no effect. 1 = input capture or output compare event occurred on channel n. 0 = no input capture or output compare event occurred on channel n. bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000 bit 7 654321 bit 0 read: chnf chnie msnb msna elsnb elsna 00 write: reset: 00000000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 169 mc9s08gb/gt chnie channel n interrupt enable this read/write bit enables interrupts from channel n. reset clears the chnie bit. 1 = channel n interrupt requests enabled. 0 = channel n interrupt requests disabled (use software polling). msnb mode select b for tpm channel n when cpwms = 0, msnb = 1 configures tpm channel n for edge-aligned pwm mode. for a summary of channel mode and setup controls, refer to table 10-3 . msna mode select a for tpm channel n when cpwms = 0 and msnb = 0, msna configures tpm channel n for input capture mode or output compare mode. refer to table 10-3 for a summary of channel mode and setup controls. if the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. elsnb:elsna edge/level select bits depending on the operating mode for the timer channel as set by cpwms:msnb:msna and shown in table 10-3 , these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the pwm output. table 10-3 mode, edge, and level selection cpwms msnb:msna elsnb:elsna mode configuration xxx 00 pin not used for tpm channel; use as an external clock for the tpm or revert to general-purpose i/o 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 01 output compare toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up)
timer/pwm (tpm) module mc9s08gb/gt 170 motorola setting elsnb:elsna to 0:0 configures the related timer pin as a general-purpose i/o pin unrelated to any timer channel functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. this is also the setting required for channel 0 when the tpmxch0 pin is used as an external clock input. 10.7.5 timer x channel value registers (tpmxcnvh:tpmxcnvl) these read/write registers contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pwm functions. the channel value registers are cleared by reset. figure 10-11 timer x channel value register high (tpmxcnvh) figure 10-12 timer x channel value register low (tpmxcnvl) in input capture mode, reading either byte (tpmxcnvh or tpmxcnvl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. this latching mechanism also resets (becomes unlatched) when the tpmxcnsc register is written. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. when both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. this latching mechanism may be manually reset by writing to the tpmxcnsc register. this latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 171 mc9s08gb/gt section 11 serial communications interface (sci) module 11.1 introduction the mc9s08gb/gt includes two independent serial communications interface (sci) modules which are sometimes called universal asynchronous receiver/transmitters (uarts). typically, these systems are used to connect to the rs232 serial input/output (i/o) port of a personal computer or workstation, and they can also be used to communicate with other embedded controllers. a flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond 115.2 kbaud. transmit and receive within the same sci use a common baud rate, and each sci module has a separate baud rate generator. this sci system offers many advanced features not commonly found on other asynchronous serial i/o peripherals on other embedded controllers. the receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. hardware parity, receiver wakeup, and double buffering on transmit and receive are also included.
serial communications interface (sci) module mc9s08gb/gt 172 motorola figure 11-1 block diagram highlighting the sci module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5 cpu bdc
data sheet ?mc9s08gb60/d v1.5 motorola 173 mc9s08gb/gt 11.2 features features of sci module include: full-duplex, standard non-return-to-zero (nrz) format double buffered transmitter and receiver with separate enables programmable baud rates (13-bit modulo divider) interrupt-driven or polled operation: transmit data register empty and transmission complete receive data register full receive overrun, parity error, framing error, and noise error idle receiver detect hardware parity generation and checking programmable 8-bit or 9-bit character length receiver wakeup by idle-line or address-mark 11.3 sci system description the sci allows full-duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus. the sci comprises of a baud rate generator, transmitter and receiver block. the transmitter and receiver operate independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following describes each of the blocks of the sci. 11.4 baud rate generation as shown in figure 11-2 , the clock source for the sci baud rate generator is the bus-rate clock. figure 11-2 sci baud rate generation sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 busclk baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
serial communications interface (sci) module mc9s08gb/gt 174 motorola sci communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mc9s08gb/gt resynchronizes to bit boundaries on every high-to-low transition, but in the worst case there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a motorola sci system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5 percent for 8-bit data format and about 4 percent for 9-bit data format. although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 11.5 transmitter functional description this section describes the overall block diagram for the sci transmitter, as well as specialized functions for sending break and idle characters. 11.5.1 transmitter block diagram figure 11-3 shows the transmitter portion of the sci.
data sheet ?mc9s08gb60/d v1.5 motorola 175 mc9s08gb/gt figure 11-3 sci transmitter block diagram the transmitter is enabled by setting the te bit in scixc2. this queues a preamble character which is one full character frame of logic high. the transmitter then remains idle (txd pin remains high) until data is available in the transmit data buffer. programs store data into the transmit data buffer by writing to the sci data register (scixd). the central element of the sci transmitter is the transmit shift register which is either 10 or 11 bits long depending on the setting in the m control bit. for the remainder of this section, we will assume m = 0, selecting the normal 8-bit data mode. in 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (tdre) status flag is set to indicate another character may be written to the transmit data buffer at scixd. h 8 7 6 5 4 3 2 1 0 l scid ?tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) enable sci controls txd txd direction to txd pin logic loop control to receive data in to txd pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd
serial communications interface (sci) module mc9s08gb/gt 176 motorola if no new character is waiting in the transmit data buffer after a stop bit is shifted out the txd pin, the transmitter sets the transmit complete flag and enters an idle mode, with txd high, waiting for more characters to transmit. writing 0 to te does not immediately release the pin to be a general-purpose i/o pin. any transmit activity that is in progress must first be completed. this includes data characters in progress, queued idle characters, and queued break characters. 11.5.2 send break and queued idle the sbk control bit in scixc2 is used to send break characters which were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (including a 0 where the stop bit would be normally). normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the sbk bit. this action queues a break character to be sent as soon as the shifter is available. if sbk is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. if the receiving device is another motorola sci, the break characters will be received as 0s in all eight (or nine) data bits and a framing error (fe = 1). when idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the te bit. this action queues an idle character to be sent as soon as the shifter is available. as long as the character in the shifter does not finish while te = 0, the sci transmitter never actually releases control of the txd pin. if there is a possibility of the shifter finishing while te = 0, set the general-purpose i/o controls so the pin that is shared with txd is an output driving a logic 1. this ensures that the txd line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. 11.6 receiver functional description in this section, the receiver block diagram ( figure 11-4 ) is used as a guide for the overall receiver functional description. next, the data sampling technique used to reconstruct receiver data is described in more detail. finally, two variations of the receiver wakeup function are explained. 11.6.1 receiver block diagram figure 11-4 shows the receiver portion of the sci.
data sheet ?mc9s08gb60/d v1.5 motorola 177 mc9s08gb/gt figure 11-4 sci receiver block diagram the receiver is enabled by setting the re bit in scixc2. character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb first), and a stop bit of logic 1. for information about 9-bit data mode, refer to 11.8.1 8- and 9-bit data modes . for the remainder of this discussion, we assume the sci is configured for normal 8-bit data mode. h 8 7 6 5 4 3 2 1 0 l scid ?rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m
serial communications interface (sci) module mc9s08gb/gt 178 motorola after receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (rdrf) status flag is set. if rdrf was already set indicating the receive data register (buffer) was already full, the overrun (or) status flag is set and the new data is lost. because the sci receiver is double buffered, the program has one full character time after rdrf is set before the data in the receive data buffer must be read to avoid a receiver overrun. when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user? program that handles receive data. refer to 11.7 interrupts and status flags for more details about flag clearing. 11.6.2 data sampling technique the sci receiver uses a 16 baud rate clock for sampling. the receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. the 16 baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. once a falling edge is located, three more samples are taken at rt3, rt5, and rt7 to make sure this was a real start bit and not just noise. if at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. the receiver then samples each bit time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is interpreted to be that of the majority of the samples taken during the bit time. in the case of the start bit, the bit is assumed to be 0 if at least two of the samples at rt3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (nf) will be set when the received character is transferred to the receive data buffer. the falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of the receiver in the presence of noise or mismatched baud rates. it does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. in the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. in the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. the receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if fe is still set.
data sheet ?mc9s08gb60/d v1.5 motorola 179 mc9s08gb/gt 11.6.3 receiver wakeup operation receiver wakeup is a hardware mechanism that allows an sci receiver to ignore the characters in a message that is intended for a different sci receiver. in such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (rwu) control bit in scixc2. when rwu = 1, it inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for handling the unimportant message characters. at the end of a message, or at the beginning of the next message, all receivers automatically force rwu to 0 so all receivers wake up in time to look at the first character(s) of the next message. 11.6.3.1 idle-line wakeup when wake = 0, the receiver is configured for idle-line wakeup. in this mode, rwu is cleared automatically when the receiver detects a full character time of the idle-line level. the m control bit selects 8-bit or 9-bit data mode which determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). the idle-line type (ilt) control bit selects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. when ilt = 1, the idle bit counter doesn? start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 11.6.3.2 address-mark wakeup when wake = 1, the receiver is configured for address-mark wakeup. in this mode, rwu is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). 11.7 interrupts and status flags the sci system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. one interrupt vector is associated with the transmitter for tdre and tc events. another interrupt vector is associated with the receiver for rdrf and idle events, and a third vector is used for or, nf, fe, and pf error conditions. each of these eight interrupt sources can be separately masked by local interrupt enable masks. the flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. the sci transmitter has two status flags that optionally can generate hardware interrupt requests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scixd. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (tc) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with txd high. this flag is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrupt enable (tcie) bit is set, a hardware interrupt will be requested whenever tc = 1. instead of hardware interrupts, software polling may be used to monitor the tdre and tc status flags if the corresponding tie or tcie local interrupt masks are 0s.
serial communications interface (sci) module mc9s08gb/gt 180 motorola when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared by reading scixs1 while rdrf = 1 and then reading scixd. when polling is used, this sequence is naturally satisfied in the normal course of the user program. if hardware interrupts are used, scixs1 must be read in the interrupt service routine (isr). normally, this is done in the isr anyway to check for receive errors, so the sequence is automatically satisfied. the idle status flag includes logic which prevents it from getting set repeatedly when the rxd line remains idle for an extended period of time. idle is cleared by reading scixs1 while idle = 1 and then reading scixd. once idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf. if the associated error was detected in the received character that caused rdrf to be set, the error flags ?noise flag (nf), framing error (fe), and parity error flag (pf) ?get set at the same time as rdrf. these flags are not set in overrun cases. if rdrf was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (or) flag gets set instead and the data and any associated nf, fe, or pf condition is lost. 11.8 additional sci functions the following sections describe additional sci functions. 11.8.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the m control bit in scixc1. in 9-bit mode, there is a ninth data bit to the left of the msb of the sci data register. for the transmit data buffer, this bit is stored in t8 in scixc3. for the receiver, the ninth bit is held in r8 in scixc3. for coherent writes to the transmit data buffer, write to the t8 bit before writing to scixd. for coherent reads of the receive data buffer, read r8 before reading scixd because reading or writing scixd is the final step in automatic clearing mechanisms for sci flags. if the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to t8 again. when data is transferred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferred from scixd to the shifter. nine-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. in custom protocols, the ninth bit can also serve as a software-controlled marker.
data sheet ?mc9s08gb60/d v1.5 motorola 181 mc9s08gb/gt 11.9 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci register data is lost and must be re-initialized upon recovery from these two stop modes. no sci module registers are affected in stop3 mode. note, because the clocks are halted, the sci module will resume operation upon exit from stop (only in stop3 mode). software should ensure stop mode is not entered while there is a character being transmitted out of or received into the sci module. 11.9.1 loop mode when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is sometimes used to check software, independent of connections in the external system to help isolate system problems. in this mode, the transmitter output is internally connected to the receiver input and the rxd pin is not used by the sci, so it reverts to a general-purpose port i/o pin. 11.9.2 single-wire operation when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). single-wire mode is used to implement a half-duplex serial connection. the receiver is internally connected to the transmitter output and to the txd pin. the rxd pin is not used and reverts to a general-purpose port i/o pin. in single-wire mode, the txdir bit in scixc3 controls the direction of serial data on the txd pin. when txdir = 0, the txd pin is an input to the sci receiver and the transmitter is temporarily disconnected from the txd pin so an external device can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the transmitter. in single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. 11.10 sci registers and control bits the sci has eight 8-bit registers to control baud rate, select sci options, report sci status, and for transmit/receive data. refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all sci registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. some mcu systems have more than one sci, so register names include placeholder characters to identify which sci is being referenced. for example, scixc1 refers to the scix control register 1 and sci2c1 is the control register 1 for sci2.
serial communications interface (sci) module mc9s08gb/gt 182 motorola 11.10.1 sci x baud rate registers (scixbdh, scixbhl) this pair of registers controls the prescale divisor for sci baud rate generation. to update the 13-bit baud rate setting [sbr12:sbr0], first write to scixbdh to buffer the high half of the new value and then write to scixbdl. the working value in scixbdh does not change until scixbdl is written. scixbdl is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled (re or te bits in scixc2 are written to 1). figure 11-5 sci baud rate register (scixbdh) figure 11-6 sci x baud rate register (scixbdl) sbr12:sbr0 baud rate modulo divisor these 13 bits are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). 11.10.2 sci x control register 1 (scixc1) this read/write register is used to control various optional features of the sci system. figure 11-7 sci x control register 1 (scixc1) bit 7 654321 bit 0 read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: reset: 00000000 = unimplemented or reserved bit 7 654321 bit 0 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset: 00000100 = unimplemented or reserved bit 7 6 54321 bit 0 read: loops sciswai rsrc m wake ilt pe pt write: reset: 0 0 000000
data sheet ?mc9s08gb60/d v1.5 motorola 183 mc9s08gb/gt loops loop mode select selects between loop back modes and normal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 1 = loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 0 = normal operation ?rxd and txd use separate pins. sciswai sci stops in wait mode 1 = sci clocks freeze while cpu is in wait mode. 0 = sci clocks continue to run in wait mode so the sci can be the source of an interrupt that wakes up the cpu. rsrc receiver source select this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 1 = single-wire sci mode where the txd pin is connected to the transmitter output and receiver input. 0 = provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd or txd pins. m 9-bit or 8-bit mode select 1 = receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. 0 = normal ?start + 8 data bits (lsb first) + stop. wake receiver wakeup method select refer to 11.6.3 receiver wakeup operation for more information. 1 = address-mark wakeup. 0 = idle-line wakeup. ilt idle line type select setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. refer to 11.6.3.1 idle-line wakeup for more information. 1 = idle character bit count starts after stop bit. 0 = idle character bit count starts after start bit. pe parity enable enables hardware parity generation and checking. when parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treated as the parity bit. 1 = parity enabled. 0 = no hardware parity generation or checking.
serial communications interface (sci) module mc9s08gb/gt 184 motorola pt parity type provided parity is enabled (pe = 1), this bit selects even or odd parity. odd parity means the total number of 1s in the data character, including the parity bit, is odd. even parity means the total number of 1s in the data character, including the parity bit, is even. 1 = odd parity. 0 = even parity. 11.10.3 sci x control register 2 (scixc2) this register can be read or written at any time. figure 11-8 sci x control register 2 (scixc2) tie transmit interrupt enable (for tdre) 1 = hardware interrupt requested when tdre flag is 1. 0 = hardware interrupts from tdre disabled (use polling). tcie transmission complete interrupt enable (for tc) 1 = hardware interrupt requested when tc flag is 1. 0 = hardware interrupts from tc disabled (use polling). rie receiver interrupt enable (for rdrf) 1 = hardware interrupt requested when rdrf flag is 1. 0 = hardware interrupts from rdrf disabled (use polling). ilie idle line interrupt enable (for idle) 1 = hardware interrupt requested when idle flag is 1. 0 = hardware interrupts from idle disabled (use polling). te transmitter enable 1 = transmitter on. 0 = transmitter off. te must be 1 in order to use the sci transmitter. normally, when te = 1, the sci forces the txd pin to act as an output for the sci system. if loops = 1 and rsrc = 0, the txd pin reverts to being a port b general-purpose i/o pin even if te = 1. when the sci is configured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traffic on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to 11.5.2 send break and queued idle for more details. bit 7 654321 bit 0 read: tie tcie rie ilie te re rwu sbk write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 185 mc9s08gb/gt when te is written to 0, the transmitter keeps control of the port txd pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose i/o pin. re receiver enable when the sci receiver is off, the rxd pin reverts to being a general-purpose port i/o pin. 1 = receiver on. 0 = receiver off. rwu receiver wakeup control this bit can be written to 1 to place the sci receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. the wakeup condition is either an idle line between messages (wake = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (wake = 1, address-mark wakeup). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to 11.6.3 receiver wakeup operation for more details. 1 = sci receiver in standby waiting for wakeup condition. 0 = normal sci receiver operation. sbk send break writing a 1 and then a 0 to sbk queues a break character in the transmit data stream. additional break characters of 10 or 11 bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relative to the information currently being transmitted, a second break character may be queued before software clears sbk. refer to 11.5.2 send break and queued idle for more details. 1 = queue break character(s) to be sent. 0 = normal transmitter operation. 11.10.4 sci x status register 1 (scixs1) this register has eight read-only status flags. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status flags. figure 11-9 sci x status register 1 (scixs1) bit 7 654321 bit 0 read: tdre tc rdrf idle or nf fe pf write: reset: 11000000 = unimplemented or reserved
serial communications interface (sci) module mc9s08gb/gt 186 motorola tdre transmit data register empty flag tdre is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. to clear tdre, read scixs1 with tdre = 1 and then write to the sci data register (scixd). 1 = transmit data register (buffer) empty. 0 = transmit data register (buffer) full. tc transmission complete flag tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 1 = transmitter idle (transmission activity complete). 0 = transmitter active (sending data, a preamble, or a break). tc is cleared automatically by reading scixs1 with tc = 1 and then doing one of the following three things. write to the sci data register (scixd) to transmit new data queue a preamble by changing te from 0 to 1 queue a break character by writing 1 to sbk in scixc2 rdrf receive data register full flag rdrf becomes set when a character transfers from the receive shifter into the receive data register (scixd). to clear rdrf, read scixs1 with rdrf = 1 and then read the sci data register (scixd). 1 = receive data register full. 0 = receive data register empty. idle idle line flag idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn? start counting idle bit times until after the stop bit. so the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scixs1 with idle = 1 and then read the sci data register (scixd). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 1 = idle line was detected. 0 = no idle line detected.
data sheet ?mc9s08gb60/d v1.5 motorola 187 mc9s08gb/gt or receiver overrun flag or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scixd yet. in this case, the new character (and all associated error information) is lost because there is no room to move it into scixd. to clear or, read scixs1 with or = 1 and then read the sci data register (scixd). 1 = receive overrun (new sci data lost). 0 = no overrun. nf noise flag the advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag nf will be set at the same time as the flag rdrf gets set for the character. to clear nf, read scixs1 and then read the sci data register (scixd). 1 = noise detected in the received character in scixd. 0 = no noise detected. fe framing error flag fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a character frame. to clear fe, read scixs1 with fe = 1 and then read the sci data register (scixd). 1 = framing error. 0 = no framing error detected. this does not guarantee the framing is correct. pf parity error flag pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scixs1 and then read the sci data register (scixd). 1 = parity error. 0 = no parity error. 11.10.5 sci x status register 2 (scixs2) this register has one read-only status flag. writes have no effect. figure 11-10 sci x status register 2 (scixs2) bit 7 654321 bit 0 read: 0000000 raf write: reset: 00000000 = unimplemented or reserved
serial communications interface (sci) module mc9s08gb/gt 188 motorola raf receiver active flag raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an idle line. this status flag can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 1 = sci receiver active (rxd input not idle). 0 = sci receiver idle waiting for a start bit. 11.10.6 sci x control register 3 (scixc3) figure 11-11 sci x control register 3 (scixc3) r8 ninth data bit for receiver when the sci is configured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the scixd register. when reading 9-bit data, read r8 before reading scixd because reading scixd completes automatic flag clearing sequences which could allow r8 and scixd to be overwritten with new data. t8 ninth data bit for transmitter when the sci is configured for 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scixd register. when writing 9-bit data, the entire 9-bit value is transferred to the sci shift register after scixd is written so t8 should be written (if it needs to change from its previous value) before scixd is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scixd is written. txdir txd pin direction in single-wire mode when the sci is configured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines the direction of data at the txd pin. 1 = txd pin is an output in single-wire mode. 0 = txd pin is an input in single-wire mode. orie overrun interrupt enable this bit enables the overrun flag (or) to generate hardware interrupt requests. 1 = hardware interrupt requested when or = 1. 0 = or interrupts disabled (use polling). bit 7 654321 bit 0 read: r8 t8 txdir 0 orie neie feie peie write: reset: 00000000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 189 mc9s08gb/gt neie noise error interrupt enable this bit enables the noise flag (nf) to generate hardware interrupt requests. 1 = hardware interrupt requested when nf = 1. 0 = nf interrupts disabled (use polling). feie framing error interrupt enable this bit enables the framing error flag (fe) to generate hardware interrupt requests. 1 = hardware interrupt requested when fe = 1. 0 = fe interrupts disabled (use polling). peie parity error interrupt enable this bit enables the parity error flag (pf) to generate hardware interrupt requests. 1 = hardware interrupt requested when pf = 1. 0 = pf interrupts disabled (use polling). 11.10.7 sci x data register (scixd) this register is actually two separate registers. reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. reads and writes of this register are also involved in the automatic flag clearing mechanisms for the sci status flags. figure 11-12 sci x data register (scixd) bit 7 654321 bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: 00000000
serial communications interface (sci) module mc9s08gb/gt 190 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 191 mc9s08gb/gt section 12 serial peripheral interface (spi) module the mc9s08gb/gt provides one serial peripheral interface (spi) module. the four pins associated with spi functionality are shared with port e pins 2?. see the electrical characteristics appendix for spi electrical parametric information. when the spi is enabled, the direction of pins is controlled by module configuration. if the spi is disabled, all four pins can be used as general-purpose i/o. figure 12-1 block diagram highlighting the spi module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5 cpu bdc
serial peripheral interface (spi) module mc9s08gb/gt 192 motorola 12.1 features features of the spi module include: master or slave mode operation full-duplex or single-wire bidirectional option programmable transmit bit rate double-buffered transmit and receive serial clock phase and polarity options slave select output selectable msb-first or lsb-first shifting 12.2 block diagrams this section includes block diagrams showing spi system connections, the internal organization of the spi module, and the spi clock dividers that control the master mode bit rate. 12.2.1 spi system block diagram figure 12-2 shows the spi modules of two mcus connected in a master-slave arrangement. the master device initiates all spi data transfers. during a transfer, the master shifts data out (on the mosi pin) to the slave while simultaneously shifting data in (on the miso pin) from the slave. the transfer effectively exchanges the data that was in the spi shift registers of the two spi systems. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input ( ss pin). in this system, the master device has configured its ss pin as an optional slave select output. figure 12-2 spi system connections 7 6 5 4 3 2 1 0 spi shifter clock generator 7 6 5 4 3 2 1 0 spi shifter ss spsck miso mosi ss spsck miso mosi master slave
data sheet ?mc9s08gb60/d v1.5 motorola 193 mc9s08gb/gt the most common uses of the spi system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial a/d or d/a converters. although figure 12-2 shows a system where data is exchanged between two mcus, many practical systems involve simpler connections where data is unidirectionally transferred from the master mcu to a slave or from a slave to the master mcu. 12.2.2 spi module block diagram figure 12-3 is a block diagram of the spi module. the central element of the spi is the spi shift register. data is written to the double-buffered transmitter (write to spid) and gets transferred to the spi shift register at the start of a data transfer. after shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from spid). pin multiplexing logic controls connections between mcu pins and the spi module. when the spi is configured as a master, the clock output is routed out to the spsck pin, the shifter output is routed to mosi, and the shifter input is routed from the miso pin. when the spi is configured as a slave, the spsck pin is routed to the clock input of the spi, the shifter output is routed to miso, and the shifter input is routed from the mosi pin. in the external spi system, simply connect all spsck pins to each other, all miso pins together, and all mosi pins together. peripheral devices often use slightly different names for these pins.
serial peripheral interface (spi) module mc9s08gb/gt 194 motorola figure 12-3 spi module block diagram tx buffer (write spid) spi shift register rx buffer (read spid) shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi (momi) miso (siso) spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie spie modfen ssoe spc0 bidiroe spibr
data sheet ?mc9s08gb60/d v1.5 motorola 195 mc9s08gb/gt 12.2.3 spi baud rate generation as shown in figure 12-4 , the clock source for the spi baud rate generator is the bus clock. the three prescale bits (sppr2:sppr1:sppr0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. the three rate select bits (spr2:spr1:spr0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal spi master mode bit-rate clock. figure 12-4 spi baud rate generation 12.3 functional description an spi transfer is initiated by checking for the spi transmit buffer empty flag (sptef = 1) and then writing a byte of data to the spi data register (spid) in the master spi device. when the spi shift register is available, this byte of data is moved from the transmit data buffer to the shifter, sptef is cleared to indicate there is room in the buffer to queue another transmit character if desired, and the spi serial transfer starts. during the spi transfer, data is sampled (read) on the miso pin at one spsck edge and shifted, changing the bit value on the mosi pin, one-half spsck cycle later. after eight spsck cycles, the data that was in the shift register of the master has been shifted out the mosi pin to the slave while eight bits of data were shifted in the miso pin into the master? shift register. at the end of this transfer, the received data byte is moved from the shifter into the receive data buffer and sprf is set to indicate the data can be read by reading spid. if another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, sptef is set, and a new transfer is started. normally, spi data is transferred most significant bit (msb) first. if the least significant bit first enable (lsbfe) bit is set, spi data is shifted lsb first. when the spi is configured as a slave, its ss pin must be driven low before a transfer starts and ss must stay low throughout the transfer. if a clock format where cpha = 0 is selected, ss must be driven to a logic 1 between successive transfers. if cpha = 1, ss may remain low between successive transfers. see 12.3.1 spi clock formats for more details. because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. the sptef flag indicates when the transmit buffer has room for a new character. the sprf flag indicates when a received character is available in the receive data buffer. the received character must be read out of the receive buffer (read spid) before the next transfer is finished or a receive overrun error results. divide by 2, 4, 8, 16, 32, 64, 128, or 256 divide by 1, 2, 3, 4, 5, 6, 7, or 8 prescaler clock rate divider sppr2:sppr1:sppr0 spr2:spr1:spr0 bus clock master spi bit rate
serial peripheral interface (spi) module mc9s08gb/gt 196 motorola in the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. there is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 12.3.1 spi clock formats to accommodate a wide variety of synchronous serial peripherals from different manufacturers, the spi system has a clock polarity (cpol) bit and a clock phase (cpha) control bit to select one of four clock formats for data transfers. cpol selectively inserts an inverter in series with the clock. cpha chooses between two different clock phase relationships between the clock and data. figure 12-5 shows the clock formats when cpha = 1. at the top of the figure, the eight bit times are shown for reference with bit 1 starting at the first spsck edge and bit 8 ending one-half spsck cycle after the sixteenth spsck edge. the msb first and lsb first lines show the order of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output from a master (provided modfen and ssoe = 1). the master ss output goes to active low one-half spsck cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave.
data sheet ?mc9s08gb60/d v1.5 motorola 197 mc9s08gb/gt figure 12-5 spi clock formats (cpha = 1) when cpha = 1, the slave begins to drive its miso output when ss goes to active low, but the data is not defined until the first spsck edge. the first spsck edge shifts the first bit of data from the shifter onto the mosi output of the master and the miso output of the slave. the next spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi inputs, respectively. at the third spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when chpa = 1, the slave? ss input is not required to go to its inactive high level between transfers. figure 12-6 shows the clock formats when cpha = 0. at the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected ( ss in goes low), and bit 8 ends at the last spsck edge. the msb first and lsb first lines show the order of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output from a master (provided modfen and ssoe = 1). the master ss output goes to active low at the start of the first bit time of the transfer and goes back high one-half spsck cycle after the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (spi) module mc9s08gb/gt 198 motorola figure 12-6 spi clock formats (cpha = 0) when cpha = 0, the slave begins to drive its miso output with the first data bit value (msb or lsb depending on lsbfe) when ss goes to active low. the first spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi inputs, respectively. at the second spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when cpha = 0, the slave? ss input must go to its inactive high level between transfers. 12.3.2 spi pin controls the spi optionally shares four port pins. the function of these pins depends on the settings of spi control bits. when the spi is disabled (spe = 0), these four pins revert to being general-purpose port i/o pins that are not controlled by the spi. 12.3.2.1 spsck ?spi serial clock when the spi is enabled as a slave, this pin is the serial clock input. when the spi is enabled as a master, this pin is the serial clock output. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
data sheet ?mc9s08gb60/d v1.5 motorola 199 mc9s08gb/gt 12.3.2.2 mosi ?master data out, slave data in when the spi is enabled as a master and spi pin control zero (spc0) is 0 (not bidirectional mode), this pin is the serial data output. when the spi is enabled as a slave and spc0 = 0, this pin is the serial data input. if spc0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data i/o pin (momi). also, the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and slave mode is selected, this pin is not used by the spi and reverts to being a general-purpose port i/o pin. 12.3.2.3 miso ?master data in, slave data out when the spi is enabled as a master and spi pin control zero (spc0) is 0 (not bidirectional mode), this pin is the serial data input. when the spi is enabled as a slave and spc0 = 0, this pin is the serial data output. if spc0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data i/o pin (siso) and the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and master mode is selected, this pin is not used by the spi and reverts to being a general-purpose port i/o pin. 12.3.2.4 ss ?slave select when the spi is enabled as a slave, this pin is the low-true slave select input. when the spi is enabled as a master and mode fault enable is off (modfen = 0), this pin is not used by the spi and reverts to being a general-purpose port i/o pin. when the spi is enabled as a master and modfen = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (ssoe = 0) or as the slave select output (ssoe = 1). 12.3.3 spi interrupts there are three flag bits, two interrupt mask bits, and one interrupt vector associated with the spi system. the spi interrupt enable mask (spie) enables interrupts from the spi receiver full flag (sprf) and mode fault flag (modf). the spi transmit interrupt enable mask (sptie) enables interrupts from the spi transmit buffer empty flag (sptef). when one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the cpu. if the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. the spi interrupt service routine (isr) should check the flag bits to determine what event caused the interrupt. the service routine should also clear the flag bit(s) before returning from the isr (usually near the beginning of the isr). 12.3.4 mode fault detection a mode fault occurs and the mode fault flag (modf) becomes set when a master spi device detects an error on the ss pin (provided the ss pin is configured as the mode fault input signal). the ss pin is configured to be the mode fault input signal when mstr = 1, mode fault enable is set (modfen = 1), and slave select output enable is clear (ssoe = 0). the mode fault detection feature can be used in a system where more than one spi device might become a master at the same time. the error is detected when a master? ss pin is low, indicating that some other spi device is trying to address this master as if it were a slave. this could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all spi output drivers when such an error is detected.
serial peripheral interface (spi) module mc9s08gb/gt 200 motorola when a mode fault is detected, modf is set and mstr is cleared to change the spi configuration back to slave mode. the output drivers on the spsck, mosi, and miso (if not bidirectional mode) are disabled. modf is cleared by reading it while it is set, then writing to the spi control register 1 (spic1). user software should verify the error condition has been corrected before changing the spi back to master mode. 12.4 spi registers and control bits the spi has five 8-bit registers to select spi options, control baud rate, report spi status, and for transmit/receive data. refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all spi registers. this section refers to registers and control bits only by their names, and a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.4.1 spi control register 1 (spic1) this read/write register includes the spi enable control, interrupt enables, and configuration options. figure 12-7 spi control register 1 (spic1) spie spi interrupt enable (for sprf and modf) this is the interrupt enable for spi receive buffer full (sprf) and mode fault (modf) events. 1 = when sprf or modf is 1, request a hardware interrupt. 0 = interrupts from sprf and modf inhibited (use polling). spe spi system enable disabling the spi halts any transfer that is in progress, clears data buffers, and initializes internal state machines. sprf is cleared and sptef is set to indicate the spi transmit data buffer is empty. 1 = spi system enabled. 0 = spi system inactive. bit 7 654321 bit 0 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: reset: 00000100
data sheet ?mc9s08gb60/d v1.5 motorola 201 mc9s08gb/gt sptie spi transmit interrupt enable this is the interrupt enable bit for spi transmit buffer empty (sptef). 1 = when sptef is 1, hardware interrupt requested. 0 = interrupts from sptef inhibited (use polling). mstr master/slave mode select 1 = spi module configured as a master spi device. 0 = spi module configured as a slave spi device. cpol clock polarity this bit effectively places an inverter in series with the clock signal from a master spi or to a slave spi device. refer to 12.3.1 spi clock formats for more details. 1 = active-low spi clock (idles high). 0 = active-high spi clock (idles low). cpha clock phase this bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. refer to 12.3.1 spi clock formats for more details. 1 = first edge on spsck occurs at the start of the first cycle of an 8-cycle data transfer. 0 = first edge on spsck occurs at the middle of the first cycle of an 8-cycle data transfer. ssoe slave select output enable this bit is used in combination with the mode fault enable (modfen) bit in spcr2 and the master/slave (mstr) control bit to determine the function of the ss pin as shown in table 12-1 . lsbfe lsb first (shifter direction) 1 = spi serial data transfers start with least significant bit. 0 = spi serial data transfers start with most significant bit. table 12-1 ss pin function modfen ssoe master mode slave mode 0 0 general-purpose i/o (not spi) slave select input 0 1 general-purpose i/o (not spi) slave select input 10 ss input for mode fault slave select input 1 1 automatic ss output slave select input
serial peripheral interface (spi) module mc9s08gb/gt 202 motorola 12.4.2 spi control register 2 (spic2) this read/write register is used to control optional features of the spi system. bits 7, 6, 5, and 2 are not implemented and always read 0. figure 12-8 spi control register 2 (spic2) modfen master mode-fault function enable when the spi is configured for slave mode, this bit has no meaning or effect. (the ss pin is the slave select input.) in master mode, this bit determines how the ss pin is used (refer to table 12-1 for more details). 1 = mode fault function enabled, master ss pin acts as the mode fault input or the slave select output. 0 = mode fault function disabled, master ss pin reverts to general-purpose i/o not controlled by spi. bidiroe bidirectional mode output enable when bidirectional mode is enabled by spi pin control 0 (spc0) = 1, bidiroe determines whether the spi data output driver is enabled to the single bidirectional spi i/o pin. depending on whether the spi is configured as a master or a slave, it uses either the mosi (momi) or miso (siso) pin, respectively, as the single spi data i/o pin. when spc0 = 0, bidiroe has no meaning or effect. 1 = spi i/o pin enabled as an output. 0 = output driver disabled so spi data i/o pin acts as an input. spiswai spi stop in wait mode 1 = spi clocks stop when the mcu enters wait mode. 0 = spi clocks continue to operate in wait mode. spc0 spi pin control 0 the spc0 bit chooses single-wire bidirectional mode. if mstr = 0 (slave mode), the spi uses the miso (siso) pin for bidirectional spi data transfers. if mstr = 1 (master mode), the spi uses the mosi (momi) pin for bidirectional spi data transfers. when spc0 = 1, bidiroe is used to enable or disable the output driver for the single bidirectional spi i/o pin. 1 = spi configured for single-wire bidirectional operation. 0 = spi uses separate pins for data input and data output. bit 7 6 54321 bit 0 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: reset: 0 0 000000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 203 mc9s08gb/gt 12.4.3 spi baud rate register (spibr) this register is used to set the prescaler and bit rate divisor for an spi master. this register may be read or written at any time. figure 12-9 spi baud rate register (spibr) sppr2:sppr1:sppr0 spi baud rate prescale divisor this 3-bit field selects one of eight divisors for the spi baud rate prescaler as shown in table 12-2 . the input to this prescaler is the bus rate clock (busclk). the output of this prescaler drives the input of the spi baud rate divider (see figure 12-4 ). bit 7 654321 bit 0 read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: reset: 00000000 = unimplemented or reserved table 12-2 spi baud rate prescaler divisor sppr2:sppr1:sppr0 prescaler divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8
serial peripheral interface (spi) module mc9s08gb/gt 204 motorola spr2:spr1:spr0 spi baud rate divisor this 3-bit field selects one of eight divisors for the spi baud rate divider as shown in table 12-3 . the input to this divider comes from the spi baud rate prescaler (see figure 12-4 ). the output of this divider is the spi bit rate clock for master mode. 12.4.4 spi status register (spis) this register has three read-only status bits. bits 6, 3, 2, 1, and 0 are not implemented and always read 0s. writes have no meaning or effect. figure 12-10 spi status register (spis) sprf spi read buffer full flag sprf is set at the completion of an spi transfer to indicate that received data may be read from the spi data register (spid). sprf is cleared by reading sprf while it is set, then reading the spi data register. 1 = data available in the receive data buffer. 0 = no data available in the receive data buffer. table 12-3 spi baud rate divisor spr2:spr1:spr0 rate divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 bit 7 654321 bit 0 read: sprf 0 sptef modf 0000 write: reset: 00100000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 205 mc9s08gb/gt sptef spi transmit buffer empty flag this bit is set when there is room in the transmit data buffer. it is cleared by reading spis with sptef set, followed by writing a data value to the transmit buffer at spid. spis must be read with sptef = 1 before writing data to spid or the spid write will be ignored. sptef generates an sptef cpu interrupt request if the sptie bit in the spic1 is also set. sptef is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. for an idle spi (no data in the transmit buffer or the shift register and no transfer in progress), data written to spid is transferred to the shifter almost immediately so sptef is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. after completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and sptef will be cleared to indicate there is room for new data in the transmit buffer. if no new data is waiting in the transmit buffer, sptef simply remains set and no data moves from the buffer to the shifter. 1 = spi transmit buffer empty. 0 = spi transmit buffer not empty. modf master mode fault flag modf is set if the spi is configured as a master and the slave select input goes low, indicating some other spi device is also configured as a master. the ss pin acts as a mode fault error input only when mstr = 1, modfen = 1, and ssoe = 0; otherwise, modf will never be set. modf is cleared by reading modf while it is 1, then writing to spi control register 1 (spic1). 1 = mode fault error detected. 0 = no mode fault error. 12.4.5 spi data register (spid) figure 12-11 spi data register (spid) reads of this register return the data read from the receive data buffer. writes to this register write data to the transmit data buffer. when the spi is configured as a master, writing data to the transmit data buffer initiates an spi transfer. data should not be written to the transmit data buffer unless the spi transmit buffer empty flag (sptef) is set, indicating there is room in the transmit buffer to queue a new transmit byte. data may be read from spid any time after sprf is set and before another transfer is finished. failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000
serial peripheral interface (spi) module mc9s08gb/gt 206 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 207 mc9s08gb/gt section 13 inter-integrated circuit (iic) module the mc9s08gb/gt series of microcontrollers provides one inter-integrated circuit (iic) module for communication with other integrated circuits. the two pins associated with this module, sda and scl share port c pins 2 and 3, respectively. all functionality as described in this section is available on mc9s08gb/gt. when the iic is enabled, the direction of pins is controlled by module configuration. if the iic is disabled, both pins can be used as general-purpose i/o. figure 13-1 block diagram highlighting the iic module ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5 cpu bdc
inter-integrated circuit (iic) module mc9s08gb/gt 208 motorola 13.1 introduction the inter-integrated circuit (iic) provides a method of communication between a number of devices. the interface is designed to operate up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. for additional detail, please refer to volume 1 of the hcs08 reference manual, (motorola document order number hcs08rmv1/d). 13.1.1 features the iic includes these distinctive features: compatible with iic bus standard multi-master operation software programmable for one of 64 different serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identification interrupt start and stop signal generation/detection repeated start signal generation acknowledge bit generation/detection bus busy detection 13.1.2 modes of operation tiic functions the same in normal and monitor modes. a brief description of the iic in the various mcu modes is given here. run mode ?this is the basic mode of operation. to conserve power in this mode, disable the module. wait mode the module will continue to operate while the mcu is in wait mode and can provide a wake-up interrupt. stop mode ?the iic is inactive in stop3 mode for reduced power consumption. the stop instruction does not affect iic register states. stop1 and stop2 will reset the register contents. 13.1.3 block diagram figure 13-2 is a block diagram of the iic.
data sheet ?mc9s08gb60/d v1.5 motorola 209 mc9s08gb/gt figure 13-2 iic functional block diagram 13.1.4 detailed signal descriptions this section describes each user-accessible pin signal. 13.1.4.1 scl ?serial clock line the bidirectional scl is the serial clock line of the iic system. 13.1.4.2 sda ?serial data line the bidirectional sda is the serial data line of the iic system 13.2 functional description this section provides a complete functional description of the iic module. input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
inter-integrated circuit (iic) module mc9s08gb/gt 210 motorola 13.2.1 iic protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. a logic and function is exercised on both lines with external pull-up resistors. the value of these resistors is system dependent. normally, a standard communication is composed of four parts: start signal slave address transmission data transfer stop signal the stop signal should not be confused with the cpu stop instruction. the iic bus system communication is described briefly in the following sections and illustrated in figure 13-3 . figure 13-3 iic bus transmission signals 13.2.1.1 start signal when the bus is free; i.e., no master device is engaging the bus (both scl and sda lines are at logical high), a master may initiate communication by sending a start signal. as shown in figure 13-3 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 99 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
data sheet ?mc9s08gb60/d v1.5 motorola 211 mc9s08gb/gt 13.2.1.2 slave address transmission the first byte of data transferred immediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pulling the sda low at the 9th clock (see figure 13-3 ). no two slaves in the system may have the same address. if the iic module is the master, it must not transmit an address that is equal to its own slave address. the iic cannot be master and slave at the same time. however, if arbitration is lost during an address cycle, the iic will revert to slave mode and operate correctly even if it is being addressed by another master. 13.2.1.3 data transfer before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device each data byte is 8 bits long. data may be changed only while scl is low and must be held stable while scl is high as shown in figure 13-3 . there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. an acknowledge is signalled by pulling the sda low at the ninth clock. in summary, one complete data transfer needs nine clock pulses. if the slave receiver does not acknowledge the master in the 9th bit time, the sda line must be left high by the slave. the master interprets the failed acknowledge as an unsuccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the sda line. in either case, the data transfer is aborted and the master does one of two things: relinquishes the bus by generating a stop signal. commences a new calling by generating a repeated start signal. 13.2.1.4 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-high transition of sda while scl at logical 1 (see figure 13-3 ). the master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus.
inter-integrated circuit (iic) module mc9s08gb/gt 212 motorola 13.2.1.5 repeated start signal as shown in figure 13-3 , a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 13.2.1.6 arbitration procedure the iic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. the losing masters immediately switch over to slave receive mode and stop driving sda output. in this case, the transition from master to slave mode does not generate a stop condition. meanwhile, a status bit is set by hardware to indicate loss of arbitration. 13.2.1.7 clock synchronization because wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. the devices start counting their low period and after a device? clock has gone low, it holds the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line if another device clock is still within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 13-4 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the device clocks and the state of the scl line and all the devices start counting their high periods. the first device to complete its high period pulls the scl line low again. figure 13-4 iic clock synchronization scl1 scl2 scl internal counter reset delay start counting high period
data sheet ?mc9s08gb60/d v1.5 motorola 213 mc9s08gb/gt 13.2.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte transfer (9 bits). in such case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 13.2.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 13.3 resets the iic is disabled after reset. the iic cannot cause an mcu reset. 13.4 interrupts the iic generates a single interrupt. an interrupt from the iic is generated when any of the events in table 13-1 occur provided the iicie bit is set. the interrupt is driven by bit iicif (of the iic status register) and masked with bit iicie (of the iic control register). the iicif bit must be cleared by software by writing a one to it in the interrupt routine. the user can determine the interrupt type by reading the status register. 13.4.1 byte transfer interrupt the tcf (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 13.4.2 address detect interrupt when its own specific address (iic address register) is matched with the calling address, the iaas bit in status register is set. the cpu is interrupted provided the iicie is set. the cpu must check the srw bit and set its tx mode accordingly. table 13-1 interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie
inter-integrated circuit (iic) module mc9s08gb/gt 214 motorola 13.4.3 arbitration lost interrupt the iic is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. the iic module asserts this interrupt when it loses the data arbitration process and the arbl bit in the status register is set. arbitration is lost in the following circumstances: sda sampled as a low when the master drives a high during an address or data transmit cycle. sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. a start cycle is attempted when the bus is busy. a repeated start cycle is requested in slave mode. a stop condition is detected when the master did not request it. this bit must be cleared by software by writing a one to it. 13.5 iic registers and control bits this section consists of the iic register descriptions in address order. refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all iic registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.5.1 iic address register (iica) figure 13-5 iic address register (iica) addr iic address register the addr contains the specific slave address to be used by the iic module. this is the address the module will respond to when addressed as a slave. bit 7 654321 bit 0 read: addr 0 write: reset: 00000000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 215 mc9s08gb/gt 13.5.2 iic frequency divider register (iicf) figure 13-6 iic frequency divider register (iicf) mult iic multiplier factor the mult bits define the multiplier factor mul. this factor is used along with the scl divider to generate the iic baud rate. table 13-2 provides the multiplier factor mul as defined by the mult bits. icr iic clock rate the icr bits are used to prescale the bus clock for bit rate selection. these bits are used to define the scl divider and the sda hold value. the scl divider multiplied by the value provided by the mult register (multiplier factor mul) is used to generate iic baud rate. iic baud rate = bus speed (hz)/(mul * scl divider) sda hold time is the delay from the falling edge of the scl (iic clock) to the changing of sda (iic data). the icr is used to determine the sda hold value. sda hold time = bus period (s) * sda hold value table 13-3 provides the scl divider and sda hold values for corresponding values of the icr. these values can be used to set iic baud rate and sda hold time. for example: bus speed = 8 mhz mult is set to 01 (mul = 2) desired iic baud rate = 100 kbps iic baud rate = bus speed (hz)/(mul * scl divider) 100000 = 8000000/(2*scl divider) scl divider = 40 table 13-3 shows that icr must be set to 0b to provide an scl divider of 40 and that this will result in an sda hold value of 9. sda hold time = bus period (s) * sda hold value sda hold time = 1/8000000 * 9 = 1.125 s bit 7 654321 bit 0 read: mult icr write: reset: 00000000 table 13-2 multiplier factor mult mul 00 01 01 02 10 04 11 reserved
inter-integrated circuit (iic) module mc9s08gb/gt 216 motorola if the generated sda hold value is not acceptable, the mult bits can be used to change the icr. this will result in a different sda hold value. table 13-3 iic divider and hold values icr (hex) scl divider sda hold value icr (hex) scl divider sda hold value 00 20 7 20 160 17 01 22 7 21 192 17 02 24 8 22 224 33 03 26 8 23 256 33 04 28 9 24 288 49 05 30 9 25 320 49 06 34 10 26 384 65 07 40 10 27 480 65 08 28 7 28 320 33 09 32 7 29 384 33 0a 36 9 2a 448 65 0b 40 9 2b 512 65 0c 44 11 2c 576 97 0d 48 11 2d 640 97 0e 56 13 2e 768 129 0f 68 13 2f 960 129 10 48 9 30 640 65 11 56 9 31 768 65 12 64 13 32 896 129 13 72 13 33 1024 129 14 80 17 34 1152 193 15 88 17 35 1280 193 16 104 21 36 1536 257 17 128 21 37 1920 257
data sheet ?mc9s08gb60/d v1.5 motorola 217 mc9s08gb/gt 13.5.3 iic control register (iicc) figure 13-7 iic control register (iicc) iicen iic enable the iicen bit determines whether the iic module is enabled. 1 = iic is enabled. 0 = iic is not enabled. iicie iic interrupt enable the iicie bit determines whether an iic interrupt is requested. 1 = iic interrupt request enabled. 0 = iic interrupt request not enabled. mst master mode select the mst bit is changed from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. when this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 1 = master mode. 0 = slave mode. 18 80 9 38 1280 129 19 96 9 39 1536 129 1a 112 17 3a 1792 257 1b 128 17 3b 2048 257 1c 144 25 3c 2304 385 1d 160 25 3d 2560 385 1e 192 33 3e 3072 513 1f 240 33 3f 3840 513 bit 7 654321 bit 0 read: iicen iicie mst tx txak 000 write: rsta reset: 00000000 = unimplemented or reserved table 13-3 iic divider and hold values (continued) icr (hex) scl divider sda hold value icr (hex) scl divider sda hold value
inter-integrated circuit (iic) module mc9s08gb/gt 218 motorola tx transmit mode select the tx bit selects the direction of master and slave transfers. in master mode this bit should be set according to the type of transfer required. therefore, for address cycles, this bit will always be high. when addressed as a slave this bit should be set by software according to the srw bit in the status register. 1 = transmit. 0 = receive. txak transmit acknowledge enable this bit specifies the value driven onto the sda during data acknowledge cycles for both master and slave receivers. 1 = no acknowledge signal response is sent. 0 = an acknowledge signal will be sent out to the bus after receiving one data byte. rsta repeat start writing a one to this bit will generate a repeated start condition provided it is the current master. this bit will always be read as a low. attempting a repeat at the wrong time will result in loss of arbitration. 13.5.4 iic status register (iics) figure 13-8 iic status register (iics) tcf transfer complete flag this bit is set on the completion of a byte transfer. note that this bit is only valid during or immediately following a transfer to the iic module or from the iic module.the tcf bit is cleared by reading the iicd register in receive mode or writing to the iicd in transmit mode. 1 = transfer complete. 0 = transfer in progress. iaas addressed as a slave the iaas bit is set when its own specific address is matched with the calling address. writing the iicc register clears this bit. 1 = addressed as a slave. 0 = not addressed. bit 7 654321 bit 0 read: tcf iaas busy arbl 0 srw iicif rxak write: reset: 10000000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 219 mc9s08gb/gt busy bus busy the busy bit indicates the status of the bus regardless of slave or master mode. the busy bit is set when a start signal is detected and cleared when a stop signal is detected. 1 = bus is busy. 0 = bus is idle. arbl arbitration lost this bit is set by hardware when the arbitration procedure is lost. the arbl bit must be cleared by software, by writing a one to it. 1 = loss of arbitration. 0 = standard bus operation. srw slave read/write when addressed as a slave the srw bit indicates the value of the r/w command bit of the calling address sent to the master. 1 = slave transmit, master reading from slave. 0 = slave receive, master writing to slave. iicif iic interrupt flag the iicif bit is set when an interrupt is pending. this bit must be cleared by software, by writing a one to it in the interrupt routine. one of the following events can set the iicif bit: one byte transfer completes match of slave address to calling address arbitration lost 1 = interrupt pending. 0 = no interrupt pending. rxak receive acknowledge when the rxak bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. if the rxak bit is high it means that no acknowledge signal is detected. 1 = no acknowledge received. 0 = acknowledge received.
inter-integrated circuit (iic) module mc9s08gb/gt 220 motorola 13.5.5 iic data i/o register (iicd) figure 13-9 iic data i/o register (iicd) data data in master transmit mode, when data is written to the iicd, a data transfer is initiated. the most significant bit is sent first. in master receive mode, reading this register initiates receiving of the next byte of data. note: when transitioning out of master receive mode, the iic mode should be switched before reading the iicd register to prevent an inadvertent initiation of a master receive data transfer. in slave mode, the same functions are available after an address match has occurred. note that the tx bit in the iicc must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is configured for master transmit but a master receive is desired, then reading the iicd will not initiate the receive. reading the iicd will return the last byte received while the iic is configured in either master receive or slave receive modes. the iicd does not reflect every byte that is transmitted on the iic bus, nor can software verify that a byte has been written to the iicd correctly by reading it back. in master transmit mode, the first byte of data written to iicd following assertion of mst is used for the address transfer and should comprise of the calling address (in bit 7?it 1) concatenated with the required r/w bit (in position bit 0). bit 7 654321 bit 0 read: data write: reset: 00000000
data sheet ?mc9s08gb60/d v1.5 motorola 221 mc9s08gb/gt section 14 analog-to-digital converter (atd) module the mc9s08gb/gt provides one 8-channel analog-to-digital (atd) module. the eight atd channels share port b. each channel individually can be configured for general-purpose i/o or for atd functionality. all features of the atd module as described in this section are available on the mc9s08gb/gt. electrical parametric information for the atd may be found in the electrical characteristics appendix. figure 14-1 mc9s08gbxx block diagram highlighting atd block and pins ptd3/tpm2ch0 ptd4/tpm2ch1 ptd5/tpm2ch2 ptd6/tpm2ch3 ptc1/rxd2 ptc0/txd2 v ss v dd pte3/miso pte2/ ss pta7/kbip7 pte0/txd1 pte1/rxd1 ptd2/tpm1ch2 ptd1/tpm1ch1 ptd0/tpm1ch0 ptc7 ptc6 ptc5 ptc4 ptc3/scl ptc2/sda port a port c port d port e 8-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi) user flash user ram (gb60 = 4096 bytes) debug module (dbg) (gb60 = 61,268 bytes) hcs08 core notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq enabled (irqpe = 1). 3. irq does not have a clamp diode to v dd . irq should not be driven above v dd . 4. pin contains integrated pullup device. 5. high current drive 6. pins pta[7:4] contain software configurable pullup/pulldown device. pulldown available when kbi enabled (kbipn = 1). note 1 note 1 3-channel timer/pwm module (tpm1) ptb7/ad7 port b pte5/spsck pte4/mosi pte6 pte7 interface module (sci2) hcs08 system control resets and interrupts modes of operation power management voltage regulator rti serial communications cop irq lvd internal bus low-power oscillator internal clock generator (icg) reset v ssad v ddad v refh v refl analog-to-digital converter (atd) interface module (sci1) serial communications 5-channel timer/pwm module (tpm2) port f ptf7?tf0 note 1 ptd7/tpm2ch4 8 pta0/kbip0 8 ptb0/ad0 8 ptg3 ptg2/extal ptg0/bkgd/ms ptg1/xtal port g ptg4 ptg6 ptg7 ptg5 note 4 notes 1, 5 (gb32 = 32,768 bytes) (gb32 = 2048 bytes) irq notes 2, 3 10-bit notes 1, 6 note 1 notes 1, 5 cpu bdc
analog-to-digital converter (atd) module mc9s08gb/gt 222 motorola 14.1 introduction the atd module is an analog-to-digital converter with a successive approximation register (sar) architecture with sample and hold. 14.1.1 features 8-/10-bit resolution 14.0 sec, 10-bit single conversion time at a conversion frequency of 2 mhz left-/right-justified result data left-justified signed data mode conversion complete flag or conversion complete interrupt generation analog input multiplexer for up to eight analog input channels single or continuous conversion mode 14.1.2 modes of operation the atd has two modes for low power stop mode power-down mode 14.1.2.1 stop mode when the mcu goes into stop mode, the mcu stops the clocks and the atd analog circuitry is turned off, placing the module into a low-power state. once in stop mode, the atd module aborts any single or continuous conversion in progress. upon exiting stop mode, no conversions occur and the registers have their previous values. as long as the atdpu bit is set prior to entering stop mode, the module is reactivated coming out of stop. 14.1.2.2 power down mode clearing the atdpu bit in register atdc also places the atd module in a low-power state. the atd conversion clock is disabled and the analog circuitry is turned off, placing the module in power-down mode. (this mode does not remove power to the atd module.) once in power-down mode, the atd module aborts any conversion in progress. upon setting the atdpu bit, the module is reactivated. during power-down mode, the atd registers are still accessible. note that the reset state of the atdpu bit is zero. therefore, the module is reset into the power-down state. 14.1.3 block diagram figure 14-2 illustrates the functional structure of the atd module.
data sheet ?mc9s08gb60/d v1.5 motorola 223 mc9s08gb/gt figure 14-2 atd block diagram address control r/w data ctl data justification interrupt conversion register sar_reg <9:0> conversion clock prescaler busclk clock prescaler ctl status state machine conversion mode control block control and registers ctl result registers input mux = internal pins = chip pads v ddad v ss v ssad v dd ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 v refl v refh analog digital powerdown successive approximation register analog-to-digital converter (atd) block status
analog-to-digital converter (atd) module mc9s08gb/gt 224 motorola 14.2 signal description 14.2.1 overview the atd supports eight input channels and requires 4 supply/reference/ground pins. these pins are listed in table 14-1 . 14.2.1.1 channel input pins ?ad7?d0 the channel pins are used as the analog input pins of the atd. each pin is connected to an analog switch which serves as the signal gate into the sample submodule. 14.2.1.2 atd reference pins ?v refh , v refl these pins serve as the source for the high and low reference potentials for the converter. separation from the power supply pins accommodates the filtering necessary to achieve the accuracy of which the system is capable. 14.2.1.3 atd supply pins ?v ddad , v ssad these two pins are used to supply power and ground to the analog section of the atd. dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on digital power supplies. note: v ddad and v dd must be at the same potential. likewise, v ssad and v ss must be at the same potential. 14.3 functional description the atd uses a successive approximation register (sar) architecture. the atd contains all the necessary elements to perform a single analog-to-digital conversion. a write to the atdsc register initiates a new conversion. a write to the atdc register will interrupt the current conversion but it will not initiate a new conversion. a write to the atdpe register will also abort the current conversion but will not initiate a new conversion. if a conversion is already running when a write to the atdsc register is made, it will be aborted and a new one will be started. table 14-1 signal properties name function ad7?d0 channel input pins v refh high reference voltage for atd converter v refl low reference voltage for atd converter v ddad atd power supply voltage v ssad atd ground supply voltage
data sheet ?mc9s08gb60/d v1.5 motorola 225 mc9s08gb/gt 14.3.1 mode control the atd has a mode control unit to communicate with the sample and hold (s/h) machine and the sar machine when necessary to collect samples and perform conversions. the mode control unit signals the s/h machine to begin collecting a sample and for the sar machine to begin receiving a sample. at the end of the sample period, the s/h machine signals the sar machine to begin the analog-to-digital conversion process. the conversion process is terminated when the sar machine signals the end of conversion to the mode control unit. for v refl and v refh , the sar machine uses the reference potentials to set the sampled signal level within itself without relying on the s/h machine to deliver them. the mode control unit organizes the conversion, specifies the input sample channel, and moves the digital output data from the sar register to the result register. the result register consists of a dual-port register. the sar register writes data into the register through one port while the module data bus reads data out of the register through the other port. 14.3.2 sample and hold the s/h machine accepts analog signals and stores them as capacitor charge on a storage node located in the sar machine. only one sample can be held at a time so the s/h machine and the sar machine can not run concurrently even though they are independent machines. figure 14-3 shows the placement of the various resistors and capacitors. figure 14-3 resistor and capacitor placement when the s/h machine is not sampling, it disables its own internal clocks.the input analog signals are unipolar. the signals must fall within the potential range of v ssad to v ddad . the s/h machine is not required to perform special conversions (i.e., convert v refl and v refh ). + r ain1 r as c as c ain r ain2 r ain3 r ainn atd sar engine channel select 0 channel select 1 channel select 2 channel select n . . . input pin input pin input pin input pin v ain
analog-to-digital converter (atd) module mc9s08gb/gt 226 motorola proper sampling is dependent on the following factors: analog source impedance (the real portion, r as ?see the electrical characteristics section) this is the resistive (or real, in the case of high frequencies) portion of the network driving the analog input voltage v ain . analog source capacitance (c as ) this is the filtering capacitance on the analog input, which (if large enough) may help the analog source network charge the atd input in the case of high r as . atd input resistance (r ain maximum value 7 k ? ) this is the internal resistance of the atd circuit in the path between the external atd input and the atd sample and hold circuit. this resistance varies with temperature, voltage, and process variation but a worst case number is necessary to compute worst case sample error. atd input capacitance (c ain ?maximum value 50 pf) ?this is the internal capacitance of the atd sample and hold circuit. this capacitance varies with temperature, voltage, and process variation but a worst case number is necessary to compute worst case sample error. atd conversion clock frequency (f atdclk maximum value 2 mhz) this is the frequency of the clock input to the atd and is dependent on the bus clock frequency and the atd prescaler. this frequency determines the width of the sample window, which is 14 atdclk cycles. input sample frequency (f samp ?see the electrical characteristics section) ?this is the frequency that a given input is sampled. delta-input sample voltage ( ? v samp ) ?this is the difference between the current input voltage (intended for conversion) and the previously sampled voltage (which may be from a different channel). in non-continuous convert mode, this is assumed to be the greater of (v refh ? ain ) and (v ain ?v refl ). in continuous convert mode, 5 lsb should be added to the known difference to account for leakage and other losses. delta-analog input voltage ( ? v ain ) this is the difference between the current input voltage and the input voltage during the last conversion on a given channel. this is based on the slew rate of the input. in cases where there is no external filtering capacitance, the sampling error is determined by the number of time constants of charging and the change in input voltage relative to the resolution of the atd: # of time constants ( ) = (14 / f atdclk ) / ((r as + r ain ) * c ain ) sampling error in lsb (e s ) = 2 n * ( ? v samp / (v refh - v refl )) * e ? the maximum sampling error (assuming maximum change on the input voltage) will be: e s = (3.6/3.6) * e ?14/((7 k + 10 k) * 50 p * 2 m)) * 1024 = 0.271 lsb in the case where an external filtering capacitance is applied, the sampling error can be reduced based on the size of the source capacitor (c as ) relative to the analog input capacitance (c ain ). ignoring the analog source impedance (r as ), c as will charge c ain to a value of: e s = 2 n * ( ? v samp / (v refh ?v refl )) * (c ain / (c ain + c as ))
data sheet ?mc9s08gb60/d v1.5 motorola 227 mc9s08gb/gt in the case of a 0.1 f c as , a worst case sampling error of 0.5 lsb is achieved regardless of r as . however, in the case of repeated conversions at a rate of f samp , r as must re-charge c as . this recharge is continuous and controlled only by r as (not r ain ), and reduces the overall sampling error to: e s = 2 n * {( ? v ain / (v refh ?v refl )) * e ? (1 / (f samp * r as * c as ) + ( ? v samp / (v refh - v refl )) * min[(c ain / (c ain + c as )), e ? (1 / (f atdclk * (r as + r ain ) * c ain ) ]} this is a worst case sampling error which does not account for r as recharging the combination of c as and c ain during the sample window. it does illustrate that high values of r as (>10 k ? ) are possible if a large c as is used and sufficient time to recharge c as is provided between samples. in order to achieve accuracy specified under the worst case conditions of maximum ? v samp and minimum c as , r as must be less than the maximum value of 10 k ? . the maximum value of 10 k ? for r as is to ensure low sampling error in the worst case condition of maximum ? v samp and minimum c as . 14.3.3 analog input multiplexer the analog input multiplexer selects one of the eight external analog input channels to generate an analog sample. the analog input multiplexer includes negative stress protection circuitry which prevents cross-talk between channels when the applied input potentials are within specification. only analog input signals within the potential range of v refl to v refh (atd reference potentials) will result in valid atd conversions. 14.3.4 atd module accuracy definitions figure 14-4 illustrates an ideal atd transfer function. the horizontal axis represents the atd input voltage in millivolts. the vertical axis the conversion result code. the atd is specified with the following figures of merit: number of bits (n) ?the number of bits in the digitized output resolution (lsb) the resolution of the atd is the step size of the ideal transfer function. this is also referred to as the ideal code width, or the difference between the transition voltages to a given code and to the next code. this unit, known as 1lsb, is equal to 1lsb = (v refh ?v refl ) / 2 n inherent quantization error (e q ) ?this is the error caused by the division of the perfect ideal straight-line transfer function into the quantized ideal transfer function with 2 n steps. this error is 1/2 lsb. differential non-linearity (dnl) ?this is the difference between the current code width and the ideal code width (1lsb). the current code width is the difference in the transition voltages to the current code and to the next code. a negative dnl means the transfer function spends less time at the current code than ideal; a positive dnl, more. the dnl cannot be less than ?.0; a dnl of greater than 1.0 reduces the effective number of bits by 1.
analog-to-digital converter (atd) module mc9s08gb/gt 228 motorola integral non-linearity (inl) ?this is the difference between the transition voltage to the current code and the transition to the corresponding code on the adjusted transfer curve. inl is a measure of how straight the line is (how far it deviates from a straight line). the adjusted ideal transition voltage is: zero scale error (e zs ) this is the difference between the transition voltage to the first valid code and the ideal transition to that code. normally, it is defined as the difference between the actual and ideal transition to code $001, but in some cases the first transition may be to a higher code. the ideal transition to any code is: full scale error (e fs ) this is the difference between the transition voltage to the last valid code and the ideal transition to that code. normally, it is defined as the difference between the actual and ideal transition to code $3ff, but in some cases the last transition may be to a lower code. the ideal transition to any code is: total unadjusted error (e tu ) this is the difference between the transition voltage to a given code and the ideal straight-line transfer function. an alternate definition (with the same result) is the difference between the actual transfer function and the ideal straight-line transfer function. this measure of error includes inherent quantization error and all forms of circuit error (inl, dnl, zero-scale, and full-scale) except input leakage error, which is not due to the atd. input leakage error (e il ) this is the error between the transition voltage to the current code and the ideal transition to that code that is the result of input leakage across the real portion of the impedance of the network that drives the analog input. this error is a system-observable error which is not inherent to the atd, so it is not added to total error. this error is: e il (in v) = input leakage * r as there are two other forms of error which are not specified which can also affect atd accuracy. these are: sampling error (e s ) ?the error due to inadequate time to charge the atd circuitry noise error (e n ) the error due to noise on v ain ,v refh ,orv refl due to either direct coupling (noise source capacitively coupled directly on the signal) or power supply (v ddad ,v ssad ,v dd , and v ss ) noise interfering with the atd? ability to resolve the input accurately. the error due to internal sources can be reduced (and specified operation achieved) by operating the atd conversion in wait mode and ceasing all io activity. reducing the error due to external sources is dependent on system activity and board layout. (current code - 1/2) 2 n adjusted ideal trans. v = * ((v refh + e fs ) - (v refl + e zs )) (current code - 1/2) ideal transition v = 2 n *(v refh ?v refl ) (current code - 1/2) ideal transition v = 2 n *(v refh ?v refl )
data sheet ?mc9s08gb60/d v1.5 motorola 229 mc9s08gb/gt figure 14-4 atd accuracy definitions 4 8 12 0 1 2 3 4 5 6 7 8 9 a b c total unadjusted ideal straight-line ideal transfer 3 2 1 lsb d code transfer function function total unadjusted inl (assumes e zs =e fs =0) error boundary negative dnl (code width <1lsb) positive dnl (code width >1lsb) error at this code 1 lsb quantization error notes: graph is for example only and may not represent actual performance
analog-to-digital converter (atd) module mc9s08gb/gt 230 motorola 14.4 resets the atd module is reset on system reset. if the system reset signal is activated, the atd registers are initialized back to their reset state and the atd module is powered down. this occurs as a function of the register file initialization; the reset definition of the atdpu bit (power down bit) is zero or disabled. the mcu places the module back into an initialized state. if the module is performing a conversion, the current conversion is terminated, the conversion complete flag is cleared, and the sar register bits are cleared. any pending interrupts are also cancelled. note that the control, test, and status registers are initialized on reset; the initialized register state is defined in the register description section of this specification. enabling the module (using the atdpu bit) does not cause the module to reset since the register file is not initialized. finally, writing to control register atdc does not cause the module to reset; the current conversion will be terminated. 14.5 interrupts the atd module originates interrupt requests and the mcu handles or services these requests. details on how the atd interrupt requests are handled can be found in the resets, interrupts, and system configuration section. the atd interrupt function is enabled by setting the atdie bit in the atdsc register. when the atdie bit is set, an interrupt is generated at the end of an atd conversion and the atd result registers (atdrh and atdrl) contain the result data generated by the conversion. if the interrupt function is disabled (atdie = 0), then the ccf flag must be polled to determine when a conversion is complete. the interrupt will remain pending as long as the ccf flag is set. the ccf bit is cleared whenever the atd status and control (atdsc) register is written. the ccf bit is also cleared whenever the atd result registers (atdrh or atdrl) are read. 14.6 atd registers and control bits the atd has seven registers which control atd functions. refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all atd registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. table 14-2 interrupt summary interrupt local enable description ccf atdie conversion complete
data sheet ?mc9s08gb60/d v1.5 motorola 231 mc9s08gb/gt 14.6.1 atd control (atdc) figure 14-5 atd control register (atdc) writes to the atd control register will abort the current conversion, but will not start a new conversion. atdpu atd power up this bit provides program on/off control over the atd, reducing power consumption when the atd is not being used. when cleared, the atdpu bit aborts any conversion in progress. 1 = atd functionality. 0 = disable the atd and enter a low-power state. djm data justification mode this bit determines how the 10-bit conversion result data maps onto the atd result register bits. when res8 is set, bit djm has no effect and the 8-bit result is always located in atdrh. for left-justified mode, result data bits 9? map onto bits 7? of atdrh, result data bits 1 and 0 map onto atdrl bits 7 and 6, where bit 7 of atdrh is the most significant bit (msb). figure 14-6 left-justified mode for right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of atdrh, result data bits 7? map onto atdrl bits 7?, where bit 1 of atdrh is the most significant bit (msb). figure 14-7 right-justified mode bit 7 654321 bit 0 read: atdpu djm res8 sgn prs write: reset: 00000000 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 atdrh atdrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 atdrh atdrl result result
analog-to-digital converter (atd) module mc9s08gb/gt 232 motorola the effect of the djm bit on the result is shown in table 14-3 . 1 = result register data is right justified. 0 = result register data is left justified. res8 atd resolution select this bit determines the resolution of the atd converter, 8-bits or 10-bits. the atd converter has the accuracy of a 10-bit converter. however, if 8-bit compatibility is required, selecting 8-bit resolution will map result data bits 9-2 onto atdrh bits 7-0. the effect of the res8 bit on the result is shown in table 14-3 . 1 = 8-bit resolution selected. 0 = 10-bit resolution selected. sgn signed result select this bit determines whether the result will be signed or unsigned data. signed data is represented as 2? complement data and is achieved by complementing the msb of the result. signed data mode can be used only when the result is left justified (djm = 0) and is not available for right-justified mode (djm = 1). when a signed result is selected, the range for conversions becomes ?12 ($200) to 511 ($1ff) for 10-bit resolution and ?28 ($80) to 127 ($7f) for 8-bit resolution. the effect of the sgn bit on the result is shown in table 14-3 . 1 = left justified result data is signed. 0 = left justified result data is unsigned. table 14-3 available result data formats prs prescaler rate select this field of bits determines the prescaled factor for the atd conversion clock. table 14-4 illustrates the divide-by operation and the appropriate range of bus clock frequencies. res8 djm sgn data formats of result analog input v refh =v dda , v refl =v ssa atdrh:atdrl v dda v ssa 1 0 0 8-bit : left justi?d : unsigned $ff:$00 $00:$00 1 0 1 8-bit : left justi?d : signed $7f:$00 $80:$00 11 x (1) notes : 1. the sgn bit is only effective when djm = 0. when djm = 1, sgn is ignored. 8-bit : left justi?d (2) : unsigned 2. 8-bit results are always in atdrh. $ff:$00 $00:$00 0 0 0 10-bit : left justi?d : unsigned $ff:$c0 $00:$00 0 0 1 10-bit : left justi?d : signed $7f:$c0 $80:$00 01 x 1 10-bit : right justi?d : unsigned $03:$ff $00:$00
data sheet ?mc9s08gb60/d v1.5 motorola 233 mc9s08gb/gt 14.6.2 atd status and control (atdsc) figure 14-8 atd status and control register (atdsc) writes to the atd status and control register clears the ccf flag, cancels any pending interrupts, and initiates a new conversion. table 14-4 clock prescaler values prs factor = (prs +1) 2 max bus clock mhz (2 mhz max atd clock) (1) notes : 1. maximum atd conversion clock frequency is 2 mhz. the max bus clock frequency is computed from the max atd conversion clock frequency times the indicated prescaler setting; i.e., for a prs of 0, max bus clock = 2 (max atd conversion clock frequency) 2 (factor) = 4 mhz. max bus clock mhz (1 mhz max atd clock) (2) 2. use these settings if the maximum desired atd conversion clock frequency is 1 mhz. the max bus clock frequency is computed from the max atd conversion clock frequency times the indicated prescaler setting; i.e., for a prs of 0, max bus clock = 1 (max atd conversion clock frequency) 2 (factor) = 2 mhz. min bus clock (3) mhz (500 khz min atd clock) 3. minimum atd conversion clock frequency is 500 khz. the min bus clock frequency is computed from the min atd conversion clock frequency times the indicated prescaler setting; i.e., for a prs of 1, min bus clock = 0.5 (min atd conversion clock frequency) 2 (factor) = 1 mhz. 0000 2421 0001 4842 0010 6 12 6 3 0011 8 16 8 4 0100 10 20 10 5 0101 12 20 12 6 0110 14 20 14 7 0111 16 20 16 8 1000 18 20 18 9 1001 20 20 20 10 1010 22 20 20 11 1011 24 20 20 12 1100 26 20 20 13 1101 28 20 20 14 1110 30 20 20 15 1111 32 20 20 16 bit 7 654321 bit 0 read: ccf atdie atdco atdch write: reset: 00000001 = unimplemented or reserved
analog-to-digital converter (atd) module mc9s08gb/gt 234 motorola ccf conversion complete flag the ccf is a read-only bit which is set each time a conversion is complete. the ccf bit is cleared whenever the atdsc register is written. it is also cleared whenever the result registers, atdrh or atdrl, are read. 1 = current conversion is complete. 0 = current conversion is not complete. atdie atd interrupt enabled when this bit is set, an interrupt is generated upon completion of an atd conversion. at this time, the result registers contain the result data generated by the conversion. the interrupt will remain pending as long as the conversion complete flag ccf is set. if the atdie bit is cleared, then the ccf bit must be polled to determine when the conversion is complete. note that system reset clears pending interrupts. 1 = atd interrupt enabled. 0 = atd interrupt disabled. atdco atd continuous conversion when this bit is set, the atd will convert samples continuously and update the result registers at the end of each conversion. when this bit is cleared, only one conversion is completed between writes to the atdsc register. 1 = continuous conversion mode. 0 = single conversion mode. atdch analog input channel select this field of bits selects the analog input channel whose signal is sampled and converted to digital codes. table 14-5 lists the coding used to select the various analog input channels. table 14-5 analog input channel select coding atdch analog input channel 00 ad0 01 ad1 02 ad2 03 ad3 04 ad4 05 ad5 06 ad6 07 ad7 08?d reserved (default to v refl ) 1e v refh 1f v refl
data sheet ?mc9s08gb60/d v1.5 motorola 235 mc9s08gb/gt 14.6.3 atd result data (atdrh, atdrl) for left-justified mode, result data bits 9? map onto bits 7? of atdrh, result data bits 1 and 0 map onto atdrl bits 7 and 6, where bit 7 of atdrh is the most significant bit (msb). figure 14-9 left-justified mode for right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of atdrh, result data bits 7? map onto atdrl bits 7?, where bit 1 of atdrh is the most significant bit (msb). figure 14-10 right-justified mode the atd 10-bit conversion results are stored in two 8-bit result registers, atdrh and atdrl. the result data is formatted either left or right justified where the format is selected using the djm control bit in the atdc register. the 10-bit result data is mapped either between atdrh bits 7? and atdrl bits 7? (left justified), or atdrh bits 1? and atdrl bits 7? (right justified). for 8-bit conversions, the 8-bit result is always located in atdrh bits 7?, and the atdrl bits read 0. for 10-bit conversions, the six unused bits always read 0. the atdrh and atdrl registers are read-only. 14.6.4 atd pin enable (atdpe) figure 14-11 atd pin enable register (atdpe) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 atdrh atdrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 0 atdrh atdrl bit 7 654321 bit 0 read: atdpe7 atdpe6 atdpe5 atdpe4 atdpe3 atdpe2 atdpe1 atdpe0 write: reset: 00000000 result result
analog-to-digital converter (atd) module mc9s08gb/gt 236 motorola the atd pin enable register allows the pins dedicated to the atd module to be configured for atd usage. a write to this register will abort the current conversion but will not initiate a new conversion. if the atdpex bit is 0 (disabled for atd usage) but the corresponding analog input channel is selected via the atdch bits, the atd will not convert the analog input but will instead convert v refl placing zeroes in the atd result registers. atdpe7-0 atd pin 7? enables 1 = pin enabled for atd usage. 0 = pin disabled for atd usage.
data sheet ?mc9s08gb60/d v1.5 motorola 237 mc9s08gb/gt section 15 development support 15.1 introduction development support systems in the hcs08 include the background debug controller (bdc) and the on-chip debug module (dbg). the bdc provides a single-wire debug interface to the target mcu that provides a convenient interface for programming the on-chip flash and other nonvolatile memories. the bdc is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoints, and single instruction trace commands. in the hcs08 family, address and data bus signals are not available on external pins (not even in test modes). debug is done through commands fed into the target mcu via the single-wire background debug interface. the debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the mcu on a cycle-by-cycle basis without having external access to the address and data signals. the alternate bdc clock source for mc9s08gb/gt is the icglclk. see the internal clock generator (icg) module section for more information about icgclk and how to select clock sources.
development support mc9s08gb/gt 238 motorola 15.2 features features of the background debug controller (bdc) include: single pin for mode selection and background communications bdc registers are not located in the memory map sync command to determine target communications rate non-intrusive commands for memory access active background mode commands for cpu register access go and trace1 commands background command can wake cpu from stop or wait modes one hardware address breakpoint built into bdc oscillator runs in stop mode, if bdc enabled cop watchdog disabled while in active background mode features of the debug module (dbg) include: two trigger comparators: two address + read/write (r/w) or one full address + data + r/w flexible 8-word by 16-bit fifo (first-in, first-out) buffer for capture information: change-of-flow addresses or event-only data two types of breakpoints: tag breakpoints for instruction opcodes force breakpoints for any address access nine trigger modes: a-only a or b a then b a and b data (full mode) a and not b data (full mode) event-only b (store data) a then event-only b (store data) inside range (a address b) outside range (address < a or address > b)
data sheet ?mc9s08gb60/d v1.5 motorola 239 mc9s08gb/gt 15.3 background debug controller (bdc) all mcus in the hcs08 family contain a single-wire background debug interface which supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: active background mode commands require that the target mcu is in active background mode (the user program is not running). active background mode commands allow the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode. non-intrusive commands can be executed at any time even while the user? program is running. non-intrusive commands allow a user to read or write mcu memory locations or access status and control registers within the background debug controller. typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. depending on the development tool vendor, this interface pod may use a standard rs232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (usb) to communicate between the host pc and the pod. the pod typically connects to the target system with ground, the bkgd pin, reset, and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. sometimes v dd can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. figure 15-1 bdm tool connector 15.3.1 bkgd pin description bkgd is the single-wire background debug interface pin. the primary function of this pin is for bidirectional serial communication of active background mode commands and data. during reset, this pin is used to select between starting in active background mode or starting the user? application program. this pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. bdc serial communications use a custom serial protocol first introduced on the m68hc12 family of microcontrollers. this protocol assumes the host knows the communication clock rate which is determined 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd
development support mc9s08gb/gt 240 motorola by the target bdc clock rate. all communication is initiated and controlled by the host which drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most significant bit first (msb first). for a detailed description of the communications protocol, refer to 15.3.2 communication details . if a host is attempting to communicate with a target mcu which has an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync response signal from which the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. unlike typical open-drain pins, the external rc time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. the custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. refer to 15.3.2 communication details for more detail. when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode. when a development system is connected, it can pull both bkgd and reset low, release reset to select active background mode rather than normal operating mode, then release bkgd. it is not necessary to reset the target mcu to communicate with it through the background debug interface. 15.3.2 communication details the bdc serial interface requires the external controller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external controller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an external controller or by the mcu. data is transferred msb first at 16 bdc clock cycles per bit (nominal speed). the interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and control register allows the user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or low level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles.
data sheet ?mc9s08gb60/d v1.5 motorola 241 mc9s08gb/gt figure 15-2 shows an external host transmitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively drives the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. since the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. figure 15-2 bdc host-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit
development support mc9s08gb/gt 242 motorola figure 15-3 shows the host receiving a logic 1 from the target hcs08 mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. the host should sample the bit level about 10 cycles after it started the bit time. figure 15-3 bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit
data sheet ?mc9s08gb60/d v1.5 motorola 243 mc9s08gb/gt figure 15-4 shows the host receiving a logic 0 from the target hcs08 mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target mcu. the host initiates the bit time but the target hcs08 finishes it. since the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 bdc clock cycles, then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 15-4 bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin
development support mc9s08gb/gt 244 motorola 15.3.3 bdc commands bdc commands are sent serially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-first using a custom bdc communications protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 15-1 shows all hcs08 bdc commands, a shorthand description of their coding structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 15-1 to describe the coding structure of the bdc commands. commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most signi?ant bit ?st) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in the target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target-to-host direction (from bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-target direction (for bdcbkpt breakpoint register)
data sheet ?mc9s08gb60/d v1.5 motorola 245 mc9s08gb/gt table 15-1 bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a (1) notes : 1. the sync command is a special operation which does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to motorola document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to motorola document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss read bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd read a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusive c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 710/d/ss/rd increment h:x by one then read memory byte located at h:x. report status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status.
development support mc9s08gb/gt 246 motorola the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to use for bdc communications until after it has analyzed the response to the sync command. to issue a sync command, the host: drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) removes all drive to the bkgd pin so it reverts to high impedance monitors the bkgd pin for the sync response pulse the target, upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal bdc communications): waits for bkgd to return to a logic high delays 16 cycles to allow the host to stop driving the high speedup pulse drives bkgd low for 128 bdc clock cycles drives a 1-cycle high speedup pulse to force a fast rise time on bkgd removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent bdc communications. typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 15.3.4 bdc hardware breakpoint the bdc includes one relatively simple hardware breakpoint which compares the cpu address bus to a 16-bit match value in the bdcbkpt register. this breakpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to enter active background mode at the first instruction boundary following any access to the breakpoint address. the tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten) control bit in the bdc status and control register (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is disabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. the on-chip debug module (dbg) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the bdc module.
data sheet ?mc9s08gb60/d v1.5 motorola 247 mc9s08gb/gt 15.4 on-chip debug system (dbg) because hcs08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the mcu. the debug system consists of an 8-stage fifo which can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. the system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage fifo. the debug module includes control and status registers that are accessible in the user? memory map. these registers are located in the high register space to avoid using valuable direct page memory space. most of the debug module? functions are used during development, and user programs rarely access any of the control and status registers for the debug module. the one exception is that the debug system can provide the means to implement a form of rom patching. this topic is discussed in greater detail in 15.4.6 hardware breakpoints . 15.4.1 comparators a and b two 16-bit comparators (a and b) can optionally be qualified with the r/w signal and an opcode tracking circuit. separate control bits allow you to ignore r/w for each comparator. the opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actually executed as opposed to only being read from memory into the instruction queue. the comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. comparators are disabled temporarily during all bdc accesses. the a comparator is always associated with the 16-bit cpu address. the b comparator compares to the cpu address or the 8-bit cpu data bus, depending on the trigger mode selected. since the cpu data bus is separated into a read data bus and a write data bus, the rwaen and rwa control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator b data bus comparisons. if rwaen = 1 (enabled) and rwa = 0 (write), the cpu? write data bus is used. otherwise, the cpu? read data bus is used. the currently selected trigger mode determines what the debugger logic does when a comparator detects a qualified match condition. a match can cause: generation of a breakpoint to the cpu storage of data bus values into the fifo starting to store change-of-flow addresses into the fifo (begin type trace) stopping the storage of change-of-flow addresses into the fifo (end type trace)
development support mc9s08gb/gt 248 motorola 15.4.2 bus capture information and fifo operation the usual way to use the fifo is to setup the trigger mode and other control options, then arm the debugger. when the fifo has filled or the debugger has stopped storing data into the fifo, you would read the information out of it in the order it was stored into the fifo. status bits indicate the number of words of valid information that are in the fifo as data is stored into it. if a trace run is manually halted by writing 0 to arm before the fifo is full (cnt = 1:0:0:0), the information is shifted by one position and the host must perform ((8 cnt) 1) dummy reads of the fifo to advance it to the first significant entry in the fifo. in most trigger modes, the information stored in the fifo consists of 16-bit change-of-flow addresses. in these cases, read dbgfh then dbgfl to get one coherent word of information out of the fifo. reading dbgfl (the low-order byte of the fifo data port) causes the fifo to shift so the next word of information is available at the fifo data port. in the event-only trigger modes (see 15.4.5 trigger modes ), 8-bit data information is stored into the fifo. in these cases, the high-order half of the fifo (dbgfh) is not used and data is read out of the fifo by simply reading dbgfl. each time dbgfl is read, the fifo is shifted so the next data value is available through the fifo data port at dbgfl. in trigger modes where the fifo is storing change-of-flow addresses, there is a delay between cpu addresses and the input side of the fifo. because of this delay, if the trigger event itself is a change-of-flow address or a change-of-flow address appears during the next two bus cycles after a trigger event starts the fifo, it will not be saved into the fifo. in the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. the fifo can also be used to generate a profile of executed instruction addresses when the debugger is not armed. when arm = 0, reading dbgfl causes the address of the most-recently fetched opcode to be saved in the fifo. to use the profiling feature, a host debugger would read addresses out of the fifo by reading dbgfh then dbgfl at regular periodic intervals. the first eight values would be discarded because they correspond to the eight dbgfl reads needed to initially fill the fifo. additional periodic reads of dbgfh and dbgfl return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 15.4.3 change-of-flow information to minimize the amount of information stored in the fifo, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. with knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-flow information stored in the fifo. for conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). because bra and brn instructions are not conditional, these events do not cause change-of-flow information to be stored in the fifo. indirect jmp and jsr instructions use the current contents of the h:x index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect jmp or jsr. for interrupts, rti, or rts, the destination address is stored in the fifo as change-of-flow information.
data sheet ?mc9s08gb60/d v1.5 motorola 249 mc9s08gb/gt 15.4.4 tag vs. force breakpoints and triggers tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the cpu. this distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed. a force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. the usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. the tag vs. force terminology is used in two contexts within the debug module. the first context refers to breakpoint requests from the debug module to the cpu. the second refers to match signals from the comparators to the debugger control logic. when a tag-type break request is sent to the cpu, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the cpu will effectively replace the tagged opcode with a bgnd opcode so the cpu goes to active background mode rather than executing the tagged instruction. when the trgsel control bit in the dbgt register is set to select tag-type operation, the output from comparator a or b is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. there is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 15.4.5 trigger modes the trigger mode controls the overall behavior of a debug run. the 4-bit trg field in the dbgt register selects one of nine trigger modes. when trgsel = 1 in the dbgt register, the output of the comparator must propagate through an opcode tracking circuit before triggering fifo actions. the begin bit in dbgt chooses whether the fifo begins storing data when the qualified trigger is detected (begin trace), or the fifo stores data in a circular fashion from the time it is armed until the qualified trigger is detected (end trigger). a debug run is started by writing a 1 to the arm bit in the dbgc register which sets the armf flag and clears the af and bf flags and the cnt bits in dbgs. a begin-trace debug run ends when the fifo gets full. an end-trace run ends when the selected trigger event occurs. any debug run can be stopped manually by writing a 0 to the arm bit or dbgen bit in dbgc. in all trigger modes except event-only modes, the fifo stores change-of-flow addresses. in event-only trigger modes, the fifo stores data in the low-order eight bits of the fifo. the begin control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. when trgsel = 1 to select opcode fetch triggers, it is not necessary to use r/w in comparisons because opcode tags would only apply to opcode fetches which are always read cycles. it would also be unusual to specify trgsel = 1 while using a full mode trigger because the opcode value is normally known at a particular address.
development support mc9s08gb/gt 250 motorola the following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. either comparator can usually be further qualified with r/w by setting rwaen (rwben) and the corresponding rwa (rwb) value to be matched against r/w. the signal from the comparator with optional r/w qualification is used to request a cpu breakpoint if brken = 1 and tag determines whether the cpu request will be a tag request or a force request. a-only ?trigger when the address matches the value in comparator a a or b ?trigger when the address matches either the value in comparator a or the value in comparator b a then b ?trigger when the address matches the value in comparator b but only after the address for another cycle matched the value in comparator a. there can be any number of cycles after the a match and before the b match. a and b data (full mode) ?this is called a full mode because address, data, and r/w (optionally) must match within the same bus cycle to cause a trigger event. comparator a checks address, the low byte of comparator b checks data, and r/w is checked against rwa if rwaen = 1. the high-order half of comparator b is not used. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the purpose of issuing the tag request to the cpu and the cpu breakpoint is issued when the comparator a address matches. a and not b data (full mode) ?address must match comparator a, data must not match the low half of comparator b, and r/w must match rwa if rwaen = 1. all three conditions must be met within the same bus cycle to cause a trigger. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the purpose of issuing the tag request to the cpu and the cpu breakpoint is issued when the comparator a address matches. event-only b (store data) ?trigger events occur each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. a then event-only b (store data) after the address has matched the value in comparator a, a trigger event occurs each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. inside range (a address b) a trigger occurs when the address is greater than or equal to the value in comparator a and less than or equal to the value in comparator b at the same time. outside range (address < a or address > b) ?a trigger occurs when the address is either less than the value in comparator a or greater than the value in comparator b.
data sheet ?mc9s08gb60/d v1.5 motorola 251 mc9s08gb/gt 15.4.6 hardware breakpoints the brken control bit in the dbgc register may be set to 1 to allow any of the trigger conditions described in 15.4.5 trigger modes to be used to generate a hardware breakpoint request to the cpu. the tag bit in dbgc controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. a tag breakpoint causes the current opcode to be marked as it enters the instruction queue. if a tagged opcode reaches the end of the pipe, the cpu executes a bgnd instruction to go to active background mode rather than executing the tagged opcode. a force-type breakpoint causes the cpu to finish the current instruction and then go to active background mode. if the background mode has not been enabled (enbdm = 1) by a serial write_control command through the bkgd pin, the cpu will execute an swi instruction instead of going to active background mode. 15.5 registers and control bits this section contains the descriptions of the bdc and dbg registers and control bits. refer to the high-page register summary in the memory section of this data sheet for the absolute address assignments for all dbg registers. this section refers to registers and control bits only by their names. a motorola-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.5.1 bdc registers and control bits the bdc has two registers: the bdc status and control register (bdcscr) is an 8-bit register containing control and status bits for the background debug controller. the bdc breakpoint match register (bdcbkpt) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have addresses and cannot be accessed by user programs). some of the bits in the bdcscr have write limitations; otherwise, these registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents the ambiguous condition of the control bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be written by the write_control serial bdc command. the clock switch (clksw) control bit may be read or written at any time. 15.5.1.1 bdc status and control register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu.
development support mc9s08gb/gt 252 motorola figure 15-5 bdc status and control register (bdcscr) enbdm enable bdm (permit active background mode) typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 1 = bdm can be made active to allow active background mode commands. 0 = bdm cannot be made active (non-intrusive commands still allowed). bdmact background mode active status this is a read-only status bit. 1 = bdm active and waiting for serial commands. 0 = bdm not active (user application program running). bkpten bdc breakpoint enable if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 1 = bdc breakpoint enabled. 0 = bdc breakpoint disabled. fts force/tag select when fts = 1, a breakpoint is requested whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagged. if this tagged opcode ever reaches the end of the instruction queue, the cpu enters active background mode rather than executing the tagged opcode. 1 = breakpoint match forces active background mode at next instruction boundary (address need not be an opcode). 0 = tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction. clksw select source for bdc communications clock clksw defaults to 0 which selects the alternate bdc clock source. 1 = mcu bus clock. 0 = alternate bdc clock source. bit 7 6 5 4321 bit 0 read: enbdm bdmact bkpten fts clksw ws wsf dvf write: normal reset: 0 0 0 00000 reset in active bdm: 1 1 0 01000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 253 mc9s08gb/gt ws wait or stop status when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force the target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host should issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 1 = target cpu is in wait or stop mode, or a background command was used to change from wait or stop to active background mode. 0 = target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active). wsf wait or stop failure status this status bit is set if a memory access command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically, the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 1 = memory access command failed because the cpu entered wait or stop mode. 0 = memory access did not conflict with a wait or stop instruction. dvf data valid failure status this status bit is not used in the mc9s08gb/gt because it does not have any slow access memory. 1 = memory access command failed because cpu was not finished with a slow memory access. 0 = memory access did not conflict with a slow memory access. 15.5.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hardware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and configure the breakpoint logic. dedicated serial bdc commands (read_bkpt and write_bkpt) are used to read and write the bdcbkpt register but is not accessible to user programs because it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for additional information about setup and use of the hardware breakpoint logic in the bdc, refer to 15.3.4 bdc hardware breakpoint . 15.5.2 system background debug force reset register (sbdfr) this register contains a single write-only control bit. a serial active background mode command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return $00.
development support mc9s08gb/gt 254 motorola figure 15-6 system background debug force reset register (sbdfr) bdfr background debug force reset a serial active background mode command such as write_byte may be used to allow an external debug host to force a target system reset. writing logic 1 to this bit forces an mcu reset. this bit cannot be written from a user program. 15.5.3 dbg registers and control bits the debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. these registers are located in the high register space of the normal memory map so they are accessible to normal application programs. these registers are rarely if ever accessed by normal user application programs with the possible exception of a rom patching mechanism that uses the breakpoint logic. 15.5.3.1 debug comparator a high register (dbgcah) this register contains compare value bits for the high-order eight bits of comparator a. this register is forced to $00 at reset and can be read at any time or written at any time unless arm = 1. 15.5.3.2 debug comparator a low register (dbgcal) this register contains compare value bits for the low-order eight bits of comparator a. this register is forced to $00 at reset and can be read at any time or written at any time unless arm = 1. 15.5.3.3 debug comparator b high register (dbgcbh) this register contains compare value bits for the high-order eight bits of comparator b. this register is forced to $00 at reset and can be read at any time or written at any time unless arm = 1. 15.5.3.4 debug comparator b low register (dbgcbl) this register contains compare value bits for the low-order eight bits of comparator b. this register is forced to $00 at reset and can be read at any time or written at any time unless arm = 1. bit 7 654321 bit 0 read: 00000000 write: bdfr (1) notes : 1. bdfr is writable only through serial active background mode debug commands, not from user programs. reset: 00010000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 255 mc9s08gb/gt 15.5.3.5 debug fifo high register (dbgfh) this register provides read-only access to the high-order eight bits of the fifo. writes to this register have no meaning or effect. in the event-only trigger modes, the fifo only stores data into the low-order byte of each fifo word, so this register is not used and will read $00. reading dbgfh does not cause the fifo to shift to the next word. when reading 16-bit words out of the fifo, read dbgfh before reading dbgfl because reading dbgfl causes the fifo to advance to the next word of information. 15.5.3.6 debug fifo low register (dbgfl) this register provides read-only access to the low-order eight bits of the fifo. writes to this register have no meaning or effect. reading dbgfl causes the fifo to shift to the next available word of information. when the debug module is operating in event-only modes, only 8-bit data is stored into the fifo (high-order half of each fifo word is unused). when reading 8-bit words out of the fifo, simply read dbgfl repeatedly to get successive bytes of data from the fifo. it isn? necessary to read dbgfh in this case. do not attempt to read data from the fifo while it is still armed (after arming but before the fifo is filled or armf is cleared) because the fifo is prevented from advancing during reads of dbgfl. this can interfere with normal sequencing of reads from the fifo. reading dbgfl while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the fifo. by reading dbgfh then dbgfl periodically, external host software can develop a profile of program execution. after eight reads from the fifo, the ninth read will return the information that was stored as a result of the first read. to use the profiling feature, read the fifo eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. the information stored into the fifo on reads of dbgfl (while the fifo is not armed) is the address of the most-recently fetched opcode. 15.5.3.7 debug control register (dbgc) this register can be read or written at any time. figure 15-7 debug control register (dbgc) dbgen debug module enable used to enable the debug module. dbgen cannot be set to 1 if the mcu is secure. 1 = dbg enabled. 0 = dbg disabled. bit 7 6 5 4321 bit 0 read: dbgen arm tag brken rwa rwaen rwb rwben write: reset: 0 0 0 00000
development support mc9s08gb/gt 256 motorola arm arm control controls whether the debugger is comparing and storing information in the fifo. a write is used to set this bit (and the armf bit) and completion of a debug run automatically clears it. any debug run can be manually stopped by writing 0 to arm or to dbgen. 1 = debugger armed. 0 = debugger not armed. tag tag/force select controls whether break requests to the cpu will be tag or force type requests. if brken = 0, this bit has no meaning or effect. 1 = cpu breaks requested as tag type requests. 0 = cpu breaks requested as force type requests. brken break enable controls whether a trigger event will generate a break request to the cpu. trigger events can cause information to be stored in the fifo without generating a break request to the cpu. for an end trace, cpu break requests are issued to the cpu when the comparator(s) and r/w meet the trigger requirements. for a begin trace, cpu break requests are issued when the fifo becomes full. trgsel does not affect the timing of cpu break requests. 1 = triggers cause a break request to the cpu. 0 = cpu break requests not enabled. rwa r/w comparison value for comparator a when rwaen = 1, this bit determines whether a read or a write access qualifies comparator a. when rwaen = 0, rwa and the r/w signal do not affect comparator a. 1 = comparator a can only match on a read cycle. 0 = comparator a can only match on a write cycle. rwaen enable r/w for comparator a controls whether the level of r/w is considered for a comparator a match. 1 = r/w is used in comparison a. 0 = r/w is not used in comparison a. rwb r/w comparison value for comparator b when rwben = 1, this bit determines whether a read or a write access qualifies comparator b. when rwben = 0, rwb and the r/w signal do not affect comparator b. 1 = comparator b can match only on a read cycle. 0 = comparator b can match only on a write cycle. rwben enable r/w for comparator b controls whether the level of r/w is considered for a comparator b match. 1 = r/w is used in comparison b. 0 = r/w is not used in comparison b.
data sheet ?mc9s08gb60/d v1.5 motorola 257 mc9s08gb/gt 15.5.3.8 debug trigger register (dbgt) this register can be read any time, but may be written only if arm = 0, except bits 4 and 5 are hardwired to 0s. figure 15-8 debug trigger register (dbgt) trgsel trigger type controls whether the match outputs from comparators a and b are qualified with the opcode tracking logic in the debug module. if trgsel is set, a match signal from comparator a or b must propagate through the opcode tracking logic and a trigger event is only signalled to the fifo logic if the opcode at the match address is actually executed. 1 = trigger if opcode at compare address is executed (tag). 0 = trigger on access to compare address (force). begin begin/end trigger select controls whether the fifo starts filling at a trigger or fills in a circular manner until a trigger ends the capture of information. in event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 1 = trigger initiates data storage (begin trace). 0 = data stored in fifo until trigger (end trace). trg3:trg2:trg1:trg0 select trigger mode selects one of nine triggering modes bit 7 6 5 4321 bit 0 read: trgsel begin 00 trg3 trg2 trg1 trg0 write: reset: 0 0 0 00000 = unimplemented or reserved
development support mc9s08gb/gt 258 motorola 15.5.3.9 debug status register (dbgs) this is a read-only status register. figure 15-9 debug status register (dbgs) af trigger match a flag af is cleared at the start of a debug run and indicates whether a trigger match a condition was met since arming. 1 = comparator a match. 0 = comparator a has not matched. bf trigger match b flag bf is cleared at the start of a debug run and indicates whether a trigger match b condition was met since arming. 1 = comparator b match. 0 = comparator b has not matched. table 15-2 trigger mode selection trg[3:0] triggering mode 0000 a-only 0001 a or b 0010 a then b 0011 event-only b (store data) 0100 a then event-only b (store data) 0101 a and b data (full mode) 0110 a and not b data (full mode) 0111 inside range: a address b 1000 outside range: address < a or address > b 1001 ?1111 no trigger bit 7 6 5 4321 bit 0 read: af bf armf 0 cnt3 cnt2 cnt1 cnt0 write: reset: 0 0 0 00000 = unimplemented or reserved
data sheet ?mc9s08gb60/d v1.5 motorola 259 mc9s08gb/gt armf arm flag while dbgen = 1, this status bit is a read-only image of the arm bit in dbgc. this bit is set by writing 1 to the arm control bit in dbgc (while dbgen = 1) and is automatically cleared at the end of a debug run. a debug run is completed when the fifo is full (begin trace) or when a trigger event is detected (end trace). a debug run can also be ended manually by writing 0 to the arm or dbgen bits in dbgc. 1 = debugger armed. 0 = debugger not armed. cnt3:cnt2:cnt1:cnt0 fifo valid count these bits are cleared at the start of a debug run and indicate the number of words of valid data in the fifo at the end of a debug run. the value in cnt does not decrement as data is read out of the fifo. the external debug host is responsible for keeping track of the count as information is read out of the fifo. table 15-3 cnt status bits cnt[3:0] valid words in fifo 0000 no valid data 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8
development support mc9s08gb/gt 260 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 261 mc9s08gb/gt appendix a electrical characteristics a.1 introduction this section contains electrical and timing specifications. a.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table a-1 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table a-1 absolute maximum ratings rating symbol value unit supply voltage v dd ?.3 to +3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) (1) , (2) , (3) notes : 1. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2. all functional non-supply pins are internally clamped to v ss and v dd . 3. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd )is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. i d 25 ma storage temperature range t stg ?5 to 150 c
electrical characteristics mc9s08gb/gt 262 motorola a.3 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: equation 1 t j = t a + (p d ja ) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: equation 2 p d = k (t j + 273 c) solving equations 1 and 2 for k gives: equation 3 k = p d (t a + 273 c) + ja (p d ) 2 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations 1 and 2 iteratively for any value of t a . table a-2 thermal characteristics rating symbol value unit temp. code operating temperature range (packaged) t a ?0 to 85 cc thermal resistance 64-pin lqfp (gb60) 42-pin sdip (gt60) 44-pin qfp (gt60) ja 65 57 118 c/w
data sheet ?mc9s08gb60/d v1.5 motorola 263 mc9s08gb/gt a.4 electrostatic discharge (esd) protection characteristics although damage from static discharge is much less common on these devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with cdf-aec-q00 stress test qualification for automotive grade integrated circuits. (http://www.aecouncil.com/) this device was qualified to aec-q100 rev e. a device is considered to have failed if, after exposure to esd pulses, the device no longer meets the device specification requirements. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. a.5 dc characteristics this section includes information about power supply requirements, i/o pin characteristics, and power supply current in various operating modes. table a-3 esd protection characteristics parameter symbol value unit esd target for machine model (mm) mm circuit description v thmm 200 v esd target for human body model (hbm) hbm circuit description v thhbm 2000 v table a-4 dc characteristics (temperature range = ?0 to 85 c ambient) parameter symbol min typical (1) max unit supply voltage (run, wait and stop modes.) 0 < f bus < 8 mhz 0 < f bus < 20 mhz v dd 1.8 2.08 3.6 3.6 v minimum ram retention supply voltage applied to v dd v ram 1.0 (2) ? low-voltage detection threshold ?high range (v dd falling) (v dd rising) v lvdh 2.08 2.16 2.1 2.19 2.2 2.27 v low-voltage detection threshold ?low range (v dd falling) (v dd rising) v lvdl 1.80 1.88 1.82 1.90 1.91 1.99 v low-voltage warning threshold ?high range (v dd falling) (v dd rising) v lvwh 2.35 2.35 2.40 2.40 2.5 v
electrical characteristics mc9s08gb/gt 264 motorola low-voltage warning threshold ?low range (v dd falling) (v dd rising) v lvwl 2.08 2.16 2.1 2.19 2.2 2.27 v power on reset (por) re-arm voltage (2) mode = stop mode = run and wait v rearm 0.20 0.50 0.30 0.80 0.40 1.2 v input high voltage (v dd > 2.3 v) (all digital inputs) v ih 0.70 v dd ? input high voltage (1.8 v v dd 2.3 v) (all digital inputs) v ih 0.85 v dd ? input low voltage (v dd > 2.3 v) (all digital inputs) v il 0.35 v dd v input low voltage (1.8 v v dd 2.3 v) (all digital inputs) v il 0.30 v dd v input hysteresis (all digital inputs) v hys 0.06 v dd ? input leakage current (per pin) v in = v dd or v ss, all input only pins |i in | 0.025 1.0 a high impedance (off-state) leakage current (per pin) v in = v dd or v ss , all input/output |i oz | 0.025 1.0 a internal pullup and pulldown resistors (3) (all port pins and irq) r pu 17.5 52.5 k ? internal pulldown resistors (port a4?7 and irq) r pd 17.5 52.5 k ? output high voltage (v dd 1.8 v) i oh = ? ma (ports a, b, d, e, and g) v oh v dd ?0.5 v output high voltage (ports c and f) i oh = ?0 ma (v dd 2.7 v) i oh = ? ma (v dd 2.3 v) i oh = ? ma (v dd 1.8 v) v dd ?0.5 maximum total i oh for all port pins |i oht | ?0ma output low voltage (v dd 1.8 v) i ol = 2.0 ma (ports a, b, d, e, and g) v ol 0.5 v output low voltage (ports c and f) i ol = 10.0 ma (v dd 2.7 v) i ol = 6 ma (v dd 2.3 v) i ol = 3 ma (v dd 1.8 v) 0.5 0.5 0.5 maximum total i ol for all port pins i olt ?0ma table a-4 dc characteristics (continued) (temperature range = ?0 to 85 c ambient) parameter symbol min typical (1) max unit
data sheet ?mc9s08gb60/d v1.5 motorola 265 mc9s08gb/gt figure a-1 pullup and pulldown typical resistor values (v dd = 3.0 v) dc injection current (4), (5), (6), (7), (8) v in < v ss , v in > v dd single pin limit total mcu limit, includes sum of all stressed pins |i ic | 0.2 5 ma ma input capacitance (all non-supply pins) (2) c in ?pf notes : 1. typicals are measured at 25 c. 2. this parameter is characterized and not tested on each device. 3. measurement condition for pull resistors: v in = v ss for pullup and v in = v dd for pulldown. 4. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. 5. all functional non-supply pins are internally clamped to v ss and v dd . 6. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7. this parameter is characterized and not tested on each device. 8. irq does not have a clamp diode to v dd . do not drive irq above v dd . table a-4 dc characteristics (continued) (temperature range = ?0 to 85 c ambient) parameter symbol min typical (1) max unit pullup resistor typicals v dd (v) pull-up resistor (k ? ) 20 25 30 35 40 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 25 c 85 c ?0 c pulldown resistor typicals v dd (v) pulldown resistance (k ? ) 20 25 30 35 40 1.8 2.3 2.8 3.3 25 c 85 c ?0 c 3.6
electrical characteristics mc9s08gb/gt 266 motorola figure a-2 typical low-side driver (sink) characteristics (ports c and f) figure a-3 typical low-side driver (sink) characteristics (ports a, b, d, e, and g) figure a-4 typical high-side driver (source) characteristics (ports c and f) typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 0102030 typi c al v ol v s v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25 c 85 c ?0 c 25 c 85 c ?0 c typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25 c 85 c ?0 c 25 c, i ol = 2 ma 85 c, i ol = 2 ma ?0 c, i ol = 2 ma typical v dd ?v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?0 ?5 ?0 ?5 ?0 ? 0 typical v dd ?v oh vs v dd at spec i oh v dd (v) v dd ?v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?0 ma i oh = ? ma i oh = ? ma v dd ?v oh (v) 25 c 85 c ?0 c 25 c 85 c ?0 c
data sheet ?mc9s08gb60/d v1.5 motorola 267 mc9s08gb/gt figure a-5 typical high-side (source) characteristics (ports a, b, d, e, and g) a.6 supply current characteristics table a-5 supply current characteristics parameter symbol v dd (v) typical (1) max (2) temp. ( c) run supply current (3) measured at (cpu clock = 2 mhz, f bus = 1 mhz) ri dd 3 1.1 ma 2.1 ma (4) 2.1 ma (4) 2.1 ma (4) 55 70 85 2 0.8 ma 1.8 ma (4) 1.8 ma (4) 1.8 ma (4) 55 70 85 run supply current (3) measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 3 6.5 ma 7.5 ma (4) 7.5 ma (4) 7.5 ma (5) 55 70 85 2 4.8 ma 5.8 ma (4) 5.8 ma (4) 5.8 ma (4) 55 70 85 stop1 mode supply current s1i dd 3 25 na 0.6 a (4) 1.8 a (4) 4.0 a (5) 55 70 85 2 20 na 500 na (4) 1.5 a (4) 3.3 a (4) 55 70 85 stop2 mode supply current s2i dd 3 550 na 3.0 a (4) 5.5 a (4) 11 a (5) 55 70 85 2 400 na 2.4 a (4) 5.0 a (4) 9.5 a (4) 55 70 85 typical v dd ?v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 1 1.2 ?0 ?5 ?0 ? 0 typical v dd ?v oh vs v dd at spec i oh v dd (v) v dd ?v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ?v oh (v) 25 c 85 c ?0 c 25 c, i oh = 2 ma 85 c, i oh = 2 ma ?0 c, i oh = 2 ma
electrical characteristics mc9s08gb/gt 268 motorola stop3 mode supply current s3i dd 3 675 na 4.3 a (4) 7.2 a (4) 17.0 a (5) 55 70 85 2 500 na 3.5 a (4) 6.2 a (4) 15.0 a (4) 55 70 85 rti adder from stop2 or stop3 (6) 3 300 na 55 70 85 2 300 na 55 70 85 lvi adder from stop3 370 a 55 70 85 260 a 55 70 85 notes : 1. typicals are measured at 25 c. see figure a-6 through figure a-9 for typical curves across voltage/temperature. 2. values given here are preliminary estimates prior to completing characterization. 3. all modules except atd active, icg configured for fbe, and does not include any dc loads on port pins 4. values are characterized but not tested on every part. 5. every unit tested to this parameter. all other values in the max column are guaranteed by characterization. 6. most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. wait mode typical is 560 a at 3 v and 422 a at 2v with f bus = 1 mhz. table a-5 supply current characteristics parameter symbol v dd (v) typical (1) max (2) temp. ( c)
data sheet ?mc9s08gb60/d v1.5 motorola 269 mc9s08gb/gt figure a-6 typical run i dd for fbe and fee modes, i dd vs v dd figure a-7 typical stop1 i dd 18 16 14 12 10 8 6 4 2 0 i dd (ma) 20 mhz, atd off , fee, 25 c 20 mhz, atd off , fbe, 25 c 8 mhz, atd off , fbe, 25 c 8 mhz, atd off , fee, 25 c 1 mhz, atd off , fee, 25 c 1 mhz, atd off , fbe, 25 c 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.8 v dd (vdc) 2.5 2 1.5 0 400 600 800 1000 1200 v dd (v) stop1 i dd (na) 25 c 200 3 3.5 70 c 85 c 4 notes: 1. clock sources and lvd are all disabled (oscsten = lvdse = 0). 2. all i/o are set as outputs and driven to v ss with no load.
electrical characteristics mc9s08gb/gt 270 motorola figure a-8 typical stop 2 i dd figure a-9 typical stop3 i dd 2.5 2 1.5 0 1 1.5 2.5 3 4 v dd (v) stop2 i dd ( a) 25 c 0.5 3 3.5 70 c 85 c 2 3.5 4 notes: 1. clock sources and lvd are all disabled (oscsten = lvdse = 0). 2. all i/o are set as outputs and driven to v ss with no load. 2.5 2 1.5 0 2 3 5 6 8 v dd (v) stop3 i dd ( a) 25 c 1 3 3.5 70 c 85 c 4 7 4 notes: 1. clock sources and lvd are all disabled (oscsten = lvdse = 0). 2. all i/o are set as outputs and driven to v ss with no load.
data sheet ?mc9s08gb60/d v1.5 motorola 271 mc9s08gb/gt a.7 atd characteristics table a-6 atd electrical characteristics (operating) num characteristic condition symbol min typical max unit 1 atd supply (1) notes : 1. v ddad must be at same potential as v dd . v ddad 1.80 3.6 v 2 atd supply current enabled i ddadrun 0.7 1.2 ma disabled (atdpu = 0 or stop) i ddadstop 0.02 0.6 a 3 differential supply voltage v dd ? ddad |v ddlt | 100 mv 4 differential ground voltage v ss ? ssad |v sdlt | 100 mv 5 reference potential, low |v refl | v ssad v reference potential, high 2.08v electrical characteristics mc9s08gb/gt 272 motorola 6 ideal resolution (1 lsb) (5) res 2.08v < v ddad < 3.6v 2.031 3.516 mv 1.80v < v ddad < 2.08v 1.758 2.031 7 differential non-linearity (6) dnl 1.80v < v ddad < 3.6v +0.5 +1.0 lsb 8 integral non-linearity (7) inl 1.80 v < v ddad < 3.6v +0.5 +1.0 lsb 9 zero-scale error (8) e zs 1.80v < v ddad < 3.6v +0.4 +1.0 lsb 10 full-scale error (9) e fs 1.80v < v ddad < 3.6v +0.4 +1.0 lsb 11 input leakage error (10) e il 1.80v < v ddad < 3.6v +0.05 +5 lsb 12 total unadjusted error (11) e tu 1.80v < v ddad < 3.6v +1.1 +2.5 lsb notes : 1. all accuracy numbers are based on processor and system being in wait state (very little activity and no io switching) and that adequate low-pass filtering is present on analog input pins (filter with 0.01 f to 0.1 f capacitor between analog input and v refl ). failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which will vary based on board layout and the type and magnitude of the activity. 2. this is the conversion time for subsequent conversions in continuous convert mode. actual conversion time for single conversions or the first conversion in continuous mode is extended by one atd clock cycle and 2 bus cycles due to starting the conversion and setting the ccf flag. the total conversion time in bus cycles for a conversion is: sc bus cycles = ((prs+1)*2) * (28+1) + 2 cc bus cycles = ((prs+1)*2) * (28) 3. r as is the real portion of the impedance of the network driving the analog input pin. values greater than this amount may not fully charge the input circuitry of the atd resulting in accuracy error. 4. analog input must be between v refl and v refh for valid conversion. values greater than v refh will convert to $3ff less the full scale error (e fs ). 5. the resolution is the ideal step size or 1lsb = (v refh ? refl )/1024 6. differential non-linearity is the difference between the current code width and the ideal code width (1lsb). the current code width is the difference in the transition voltages to and from the current code. 7. integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition voltage for the current code. the adjusted ideal transition voltage is (current code?/2)*(1/((v refh +e fs )?v refl +e zs ))). 8. zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. the ideal transition voltage to a given code is (code?/2)*(1/(v refh ? refl )). 9. full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. the ideal transition voltage to a given code is (code?/2)*(1/(v refh ? refl )). 10. input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin. reducing the impedance of the network reduces this error. 11. total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line transfer function. this measure of error includes inherent quantization error (1/2lsb) and circuit error (differential, integral, zero-scale, and full-scale) error. the specified value of e t assumes zero e il (no leakage or zero real source impedance). table a-7 atd timing/performance characteristics (1) (continued) num characteristic symbol condition min typ max unit
data sheet ?mc9s08gb60/d v1.5 motorola 273 mc9s08gb/gt a.8 internal clock generation module characteristics table a-8 icg dc electrical speci?ations (temperature range = ?0 to 85 c ambient) characteristic symbol min typ (1) notes : 1. data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max unit load capacitors c 1 c 2 (2) 2. see crystal or resonator manufacturer? recommendation. feedback resistor low range (32k to 100 khz) high range (1m ?16 mhz) r f 10 1 m ? m ? series resistor low range (32k to 100 khz) high range (1m ?16 mhz) r s 0 0 0 0 10 0 k ? k ? icg extal xtal crystal or resonator (see note) r s c 2 r f c 1 use fundamental mode crystal or ceramic resonator only. note:
electrical characteristics mc9s08gb/gt 274 motorola a.8.1 icg frequency specifications table a-9 icg frequency speci?ations (v dda = v dda (min) to v dda (max), temperature range = ?0 to 85 c ambient) characteristic symbol min typical max unit oscillator crystal or resonator (refs = 1) (fundamental mode crystal or ceramic resonator) low range high range, fll bypassed external (clks = 10) high range, fll engaged external (clks = 11) f lo f hi_byp f hi_eng 32 1 2 100 16 10 khz mhz mhz input clock frequency (clks = 11, refs = 0) low range high range f lo f hi_eng 32 2 100 10 khz mhz input clock frequency (clks = 10, refs = 0) f extal 0 40 mhz internal reference frequency (untrimmed) f icgirclk 182.25 243 303.75 khz duty cycle of input clock (refs = 0) t dc 40 60 % output clock icgout frequency clks = 10, refs = 0 all other cases f icgout f extal (min) f lo (min) f extal (max) f icgdclkmax (max) mhz minimum dco clock (icgdclk) frequency f icgdclkmin 8 mhz maximum dco clock (icgdclk) frequency f icgdclkmax 40 mhz self-clock mode (icgout) frequency (1) notes : 1. self-clocked mode frequency is the frequency that the dco generates when the fll is open-loop. f self f icgdclkmin f icgdclkmax mhz self-clock mode reset (icgout) frequency f self_reset 5.5 8 10.5 mhz loss of reference frequency (2) low range high range 2. loss of reference frequency is the reference frequency detected internally, which transitions the icg into self-clocked mode if it is not in the desired range. f lor 5 50 25 500 khz loss of dco frequency (3) f lod 0.5 1.5 mhz crystal start-up time (4), (5) low range high range t cstl t csth 430 4 ms fll lock time (6) low range high range t lockl t lockh 2 2 ms fll frequency unlock range n unlock ?*n 4*n counts fll frequency lock range n lock ?*n 2*n counts icgout period jitter, (7) measured at f icgout max long term jitter (averaged over 2 ms interval) c jitter 0.2 % f icg
data sheet ?mc9s08gb60/d v1.5 motorola 275 mc9s08gb/gt a.9 ac characteristics this section describes ac timing characteristics for each peripheral system. for detailed information about how clocks for the bus are generated, see the internal clock generator (icg) module section. a.9.1 control timing 3. loss of dco frequency is the dco frequency detected internally, which transitions the icg into fll bypassed external mode (if an external reference exists) if it is not in the desired range. 4. this parameter is characterized before qualification rather than 100% tested. 5. proper pc board layout procedures must be followed to achieve specifications. 6. this specification applies to the period of time required for the fll to lock after entering fll engaged internal or external modes. if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f icgout . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dda and v ssa and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table a-10 control timing parameter symbol min typical max unit bus frequency (t cyc = 1/f bus )f bus dc 20 mhz real time interrupt internal oscillator f rti 700 1300 hz external reset pulse width (1) notes : 1. this is the shortest pulse that is guaranteed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 1.5 x f self_reset ?s reset low drive (2) 2. when any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f self_reset and then samples the level on the reset pin about 38 cycles later to distinguish external reset requests from internal requests. t rstdrv 34 x f self_reset ?s active background debug mode latch setup time t mssu 25 ns active background debug mode latch hold time t msh 25 ns irq pulse width (3) 3. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. t ilih 1.5 x t cyc ?s port rise and fall time (load = 50 pf) (4) slew rate control disabled slew rate control enabled 4. timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?0 c to 85 c. t rise , t fall 3 30 ns
electrical characteristics mc9s08gb/gt 276 motorola figure a-10 reset timing figure a-11 active background debug mode latch timing figure a-12 irq timing a.9.2 timer/pwm (tpm) module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. table a-11 tpm input timing function symbol min max unit external clock frequency f tpmext dc f bus /4 mhz external clock period t tpmext 4 t cyc external clock high time t clkh 1.5 t cyc external clock low time t clkl 1.5 t cyc input capture pulse width t icpw 1.5 t cyc t extrst reset pin bkgd/ms reset t mssu t msh t ilih irq
data sheet ?mc9s08gb60/d v1.5 motorola 277 mc9s08gb/gt figure a-13 timer external clock figure a-14 timer input capture pulse a.9.3 spi timing table a-12 and figure a-15 through figure a-18 describe the timing requirements for the spi system. table a-12 spi timing no. function symbol min max unit operating frequency master slave f op f bus /2048 dc f bus /4 f bus /4 hz 1 sck period master slave t sck 4 4 2048 t cyc t cyc 2 enable lead time master slave t lead 1 / 2 1 t sck t cyc 3 enable lag time master slave t lag 1 / 2 1 t sck t cyc 4 clock (sck) high or low time master slave t wsck t cyc ?30 t cyc ?30 1024 t cyc ns ns 5 data setup time (inputs) master slave t su 15 15 ns ns 6 data hold time (inputs) master slave t hi 0 25 ns ns t text t clkh t clkl tpmxchn t icpw tpmxchn t icpw tpmxchn
electrical characteristics mc9s08gb/gt 278 motorola figure a-15 spi master timing (cpha = 0) 7 slave access time t a ?t cyc 8 slave miso disable time t dis ?t cyc 9 data valid (after sck edge) master slave t v 25 25 ns ns 10 data hold time (outputs) master slave t ho 0 0 ns ns 11 rise time input output t ri t ro t cyc ?25 25 ns ns 12 fall time input output t fi t fo t cyc ?25 25 ns ns table a-12 spi timing (continued) no. function symbol min max unit sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 9 10 11 12 4 9
data sheet ?mc9s08gb60/d v1.5 motorola 279 mc9s08gb/gt figure a-16 spi master timing (cpha = 1) figure a-17 spi slave timing (cpha = 0) sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in master msb out (2) master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss (1) (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10 sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10
electrical characteristics mc9s08gb/gt 280 motorola figure a-18 spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12
data sheet ?mc9s08gb60/d v1.5 motorola 281 mc9s08gb/gt a.10 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the memory section. table a-13 flash characteristics characteristic symbol min typical max unit supply voltage for program/erase v prog/erase 2.1 3.6 v supply voltage for read operation 0 < f bus < 8 mhz 0 < f bus < 20 mhz v read 1.8 2.08 3.6 3.6 v internal fclk frequency (1) notes : 1. the frequency of this clock is controlled by a software setting. f fclk 150 200 khz internal fclk period (1/fclk) t fcyc 5 6.67 s byte program time (random location) (2) t prog 9 t fcyc byte program time (burst mode) (2) t burst 4 t fcyc page erase time (2) 2. these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc mass erase time (2) t mass 20,000 t fcyc program/erase endurance (3) t l to t h = ?0 c to + 85 c t = 25 c 3. typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how motorola defines typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory . 10,000 100,000 cycles data retention (4) 4. typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how motorola defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 years
electrical characteristics mc9s08gb/gt 282 motorola
data sheet ?mc9s08gb60/d v1.5 motorola 283 mc9s08gb/gt appendix b ordering information and mechanical drawings b.1 ordering information this section contains ordering numbers for mc9s08gb60, mc9s08gb32, MC9S08GT60, and mc9s08gt32 devices. see below for an example of the device numbering system. temperature and package designators: c = ?0 c to 85 c fu = 64-pin low quad flat package (lqfp) fb = 44-pin quad flat package (qfp) b = 42-pin skinny dual in-line package (sdip) mc = fully qualified b.2 mechanical drawings this appendix contains mechanical specifications for mc9s08gb/gt mcu. table 15-4 mc order number flash memory ram tpm available package type (part number suffix) mc9s08gb60 60k 4k one 3-channel and one 5-channel 16-bit timer 64 lqfp (fu) mc9s08gb32 32k 2k one 3-channel and one 5-channel 16-bit timer 64 lqfp (fu) MC9S08GT60 60k 4k two 2-channel/16-bit timers 44 qfp (fb) 42 sdip (b) mc9s08gt32 32k 2k two 2-channel/16-bit timers 44 qfp (fb) 42 sdip (b) mc 9 s08 gb60 c xx package designator temperature range family memory status core
ordering information and mechanical drawings mc9s08gb/gt 284 motorola b.3 64-pin lqfp package drawing case 840f-02 issue b date 09/16/98 ab ab e/2 e 60x x=a, b or d c l view y s 0.05 q q q 1 (2) 0.25 gage plane seating plane a2 (s) r1 2x r (l1) (l2) l a1 view aa b1 section ab-ab b c1 c plating base metal rotated 90 clockwise a-b m 0.08 d c 64 0.2 h a-b d 1 49 48 17 16 32 33 b e/2 e e1 d1 d/2 d d1/2 3x view y a 4x view aa 0.08 c q ( 3) 4x 4x 4x 16 tips 0.2 c a-b d e1/2 a d c h x dim min max millimeters a --- 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 d 12.00 bsc d1 10.00 bsc e 0.50 bsc e 12.00 bsc e1 10.00 bsc l 0.45 0.75 l1 1.00 ref l2 0.50 ref r1 0.10 0.20 s 0.20 ref q 07 q 0 --- q 12 ref q 12 ref n otes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane datum h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane datum c. 5. dimensions d and e to be determined at seating plane datum c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 per side. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.35. minimum space between protrusion and adjacent lead or protrusion 0.07. 1 2 3
data sheet ?mc9s08gb60/d v1.5 motorola 285 mc9s08gb/gt b.4 44-pin qfp package drawing notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. l 33 34 23 22 44 111 12 detail a -d- -a- a s a-b m 0.20 (0.008) d s c s a-b m 0.20 (0.008) d s h 0.05 (0.002) a-b s b s a-b m 0.20 (0.008) d s c s a-b m 0.20 (0.008) d s h 0.05 (0.002) a-b v l -b- -c- seating plane m m e h g c -h- datum plane detail c 0.01 (0.004) m -h- datum plane t r k q w x detail c case 824a-01 issue o date 11/19/90 dim min max min max inches millimeters a 9.90 10.10 0.390 0.398 b 9.90 10.10 0.390 0.398 c 2.10 2.45 0.083 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.10 0.079 0.083 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h --- 0.25 --- 0.010 j 0.013 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 8.00 ref 0.315 ref m 510 510 n 0.13 0.17 0.005 0.007 q 0707 r 0.13 0.30 0.005 0.012 s 12.95 13.45 0.510 0.530 t 0.13 --- 0.005 --- u 0 --- 0 --- v 12.95 13.45 0.510 0.530 w 0.40 --- 0.016 --- x 1.6 ref 0.063 ref detail a b b -a-, -b-, -d- s a-b m 0.20 (0.008) d s c f n section b-b j d base metal
ordering information and mechanical drawings mc9s08gb/gt 286 motorola b.5 42-pin sdip package drawing -a- 121 42 22 -b- seating plane -t- s a m 0.25 (0.010) t s b m 0.25 (0.010) t l h m j 42 pl d 42 pl f g n k c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010). dim min max min max millimeters inches a 1.435 1.465 36.45 37.21 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.56 f 0.032 0.046 0.81 1.17 g 0.070 bsc 1.778 bsc h 0.300 bsc 7.62 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.600 bsc 15.24 bsc m 015 015 n 0.020 0.040 0.51 1.02 case 858-01 issue o date 02/27/90
data sheet ?mc9s08gb60/d v1.5 motorola 287 mc9s08gb/gt data sheet end sheet need need more than 13 words type on blank page or will turn page landscape in pdf file?? turned white so this would not show up on customer page.
mc9s08gb/gt 288 motorola final page of 288 pages

how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003 mc9s08 gb 60/d r e v . 1. 5

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